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Total properties:
35
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Patent #:
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|
Issue Dt:
|
10/20/1987
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Application #:
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06622450
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Filing Dt:
|
06/20/1984
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Title:
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DIAGNOSTIC CIRCUIT
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|
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Patent #:
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|
Issue Dt:
|
10/28/1986
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Application #:
|
06622451
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Filing Dt:
|
06/20/1984
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Title:
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COMPUTER SYSTEM
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/05/1987
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Application #:
|
06622459
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Filing Dt:
|
06/20/1984
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Title:
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READ/MODIFY/WRITE CIRCUIT FOR COMPUTER MEMORY OPERATION
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|
|
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Patent #:
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|
Issue Dt:
|
02/24/1987
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Application #:
|
06622562
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Filing Dt:
|
06/20/1984
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Title:
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PHYSICAL CACHE UNIT FOR COMPUTER
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|
|
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Patent #:
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|
Issue Dt:
|
11/03/1987
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Application #:
|
06622740
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Filing Dt:
|
06/20/1984
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|
Title:
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AUXILIARY POWER CONNECTOR AND COMMUNICATION CHANNEL CONTROL CIRCUIT
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|
|
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Patent #:
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|
Issue Dt:
|
07/17/1990
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Application #:
|
06796745
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Filing Dt:
|
11/12/1985
|
|
Title:
|
PHYSICAL CACHE UNIT FOR COMPUTER
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|
|
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Patent #:
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|
Issue Dt:
|
03/14/1989
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Application #:
|
07088470
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Filing Dt:
|
08/19/1987
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Title:
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MICROCODE COMPUTER HAVING DISPATCH AND MAIN CONTROL STORES FOR STORING THE FIRST AND THE REMAINING MICROINSTRUCTIONS OF MACHINE INSTRUCTIONS
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|
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Patent #:
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|
Issue Dt:
|
07/26/1988
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Application #:
|
07107841
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Filing Dt:
|
10/01/1987
|
|
Title:
|
INTERMIXING OF DIFFERENT CAPACITY MEMORY ARRAY UNITS IN A COMPUTER
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/10/1989
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Application #:
|
07133195
|
Filing Dt:
|
12/15/1987
|
|
Title:
|
INSTRUCTION PROCESSING UNIT FOR COMPUTER
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|
|
|
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Patent #:
|
|
Issue Dt:
|
02/28/1989
|
Application #:
|
07147112
|
Filing Dt:
|
01/21/1988
|
|
Title:
|
CONCURRENT PROCESSING OF DATA OPERANDS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/17/1991
|
Application #:
|
07161768
|
Filing Dt:
|
02/29/1988
|
|
Title:
|
MULTI-PROCESSOR COMPUTER SYSTEM HAVING SELF-ALLOCATING PROCESSORS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/1990
|
Application #:
|
07183355
|
Filing Dt:
|
04/12/1988
|
|
Title:
|
HIERARCHICAL MEMORY SYSTEM WITH LOGICAL CACHE, PHYSICAL CACHE, AND ADDRESS TRANSLATION UNIT FOR GENERATING A SEQUENCE OF PHYSICAL ADDRESSES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/19/1989
|
Application #:
|
07206962
|
Filing Dt:
|
06/09/1988
|
|
Title:
|
INPUT/OUTPUT BUS SYSTEM WHICH GENERATES A NEW HEADER PARCEL WHEN AN INTERRUPTED DATA BLOCK TRANSFER BETWEEN A COMPUTER AND PERIPHERALS IS RESUMED
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/1991
|
Application #:
|
07293967
|
Filing Dt:
|
01/06/1989
|
|
Title:
|
DISK DRIVE INSERTION AND REMOVAL INTERLOCK
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/1989
|
Application #:
|
07328798
|
Filing Dt:
|
03/24/1989
|
|
Title:
|
MEMORY ARRAY UNIT FOR COMPUTER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/1994
|
Application #:
|
07647408
|
Filing Dt:
|
01/29/1991
|
|
Title:
|
ERROR DETECTING METHOD AND APPARATUS FOR COMPUTER MEMORY HAVING MULTI- BIT OUTPUT MEMORY CIRCUITS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/1992
|
Application #:
|
07666038
|
Filing Dt:
|
03/07/1991
|
|
Title:
|
MULTI-PROCESSOR COMPUTER SYSTEM HAVING [SELF-ALLOCATING PROCESSORS] PROCESS-INDEPENDENT COMMUNICATION REGISTER ADDRESSING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/1994
|
Application #:
|
07893761
|
Filing Dt:
|
06/05/1992
|
|
Title:
|
DEBUGGER PROGRAM WHICH INCLUDES CORRELATION OF COMPUTER PROGRAM SOURCE CODE WITH OPTIMIZED OBJECT CODE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/1995
|
Application #:
|
08109650
|
Filing Dt:
|
08/20/1993
|
|
Title:
|
METHOD AND APPARATUS FOR DELIVERING POWER USING A MULTIPLANE POWER VIA MATRIX
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|
|
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|
Patent #:
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|
Issue Dt:
|
05/02/1995
|
Application #:
|
08111106
|
Filing Dt:
|
08/24/1993
|
|
Title:
|
APPARATUS AND METHOD FOR COOLING ELECTRONIC DEVICES
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|
Patent #:
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|
Issue Dt:
|
05/13/1997
|
Application #:
|
08161937
|
Filing Dt:
|
12/03/1993
|
|
Title:
|
APPARATUS SYSTEMS AND METHODS FOR CONTROLLING ELECTRONIC MEMORIES
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Patent #:
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|
Issue Dt:
|
09/24/1996
|
Application #:
|
08167663
|
Filing Dt:
|
12/15/1993
|
|
Title:
|
SCALABLE PARALLEL PROCESSING SYSTEMS WHEREIN EACH HYPERNODE HAS PLURAL PROCESSING MODULES INTERCONNECTED BY CROSSBAR AND EACH PROCESSING MODULE HAS SCI CIRCUITRY FOR FORMING MULTI-DIMENSIONAL NETWORK WITH OTHER HYPERNODES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/1996
|
Application #:
|
08168067
|
Filing Dt:
|
12/15/1993
|
|
Title:
|
SYSTEM FOR ACCESSING DISTRIBUTED MEMORY BY BREAKING EACH ACCEPTED ACCESS REQUEST INTO SERIES OF INSTRUCTIONS BY USING SETS OF PARAMETERS DEFINED AS LOGICAL CHANNEL CONTEXT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/1996
|
Application #:
|
08168531
|
Filing Dt:
|
12/15/1993
|
|
Title:
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PARALLEL PROCESSING COMPUTER SYSTEM INTERCONNECTING UTILIZING UNIDIRECTIONAL COMMUNICATION LINKS WITH SEPARATE REQUEST AND RESPONSE LINES FOR DIRECT COMMUNICATION OR USING A CROSSBAR SWITCHING DEVICE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/19/1996
|
Application #:
|
08188154
|
Filing Dt:
|
01/27/1994
|
|
Title:
|
SCANNING, CIRCUITS, SYSTEMS AND METHODS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/25/1996
|
Application #:
|
08199686
|
Filing Dt:
|
02/22/1994
|
|
Title:
|
SYSTEMS AND METHODS FOR PROTECTING SOFTWARE FROM UNLICENSED COPYING AND USE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/11/1995
|
Application #:
|
08201009
|
Filing Dt:
|
02/24/1994
|
|
Title:
|
APPARATUS, SYSTEMS AND METHODS FOR ADDRESSING ELECTRONIC MEMORIES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/05/1995
|
Application #:
|
08218076
|
Filing Dt:
|
03/25/1994
|
|
Title:
|
LAND GRID ARRAY PACKAGE/CIRCUIT BOARD ASSEMBLIES AND METHODS FOR CONSTUCTING THE SAME
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|
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Patent #:
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|
Issue Dt:
|
12/31/1996
|
Application #:
|
08258761
|
Filing Dt:
|
06/13/1994
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR PREVENTING QUEUE OVERFLOW IN DATA PROCESSING SYSTEMS
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Patent #:
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|
Issue Dt:
|
09/21/1999
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Application #:
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08536196
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Filing Dt:
|
09/29/1995
|
|
Title:
|
COMPUTER PROGRAM DEBUGGING IN THE PRESENCE OF COMPILER SYNTHESIZED VARIABLES
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Patent #:
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|
Issue Dt:
|
07/30/1996
|
Application #:
|
08545058
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Filing Dt:
|
10/19/1995
|
|
Title:
|
APPARATUS, SYSTEMS AND METHODS FOR ISOLATING FAULTS DURING DATA TRANSMISSION USING PARITY
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Patent #:
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|
Issue Dt:
|
11/17/1998
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Application #:
|
08563334
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Filing Dt:
|
11/28/1995
|
|
Title:
|
SYSTEM AND METHOD FOR PROFILING CODE ON SYMMETRIC MULTIPROCESSOR ARCHITECTURES
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Patent #:
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|
Issue Dt:
|
12/01/1998
|
Application #:
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08663872
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Filing Dt:
|
06/19/1996
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Title:
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SYSTEM AND METHODS FOR PERFORMING CACHE LATENCY DIAGNOSTICS IN SCALABLE PARALLEL PROCESSING ARCHITECTURES INCLUDING CALCULATING CPU IDLE TIME AND COUNTING NUMBER OF CACHE MISSES
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Patent #:
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|
Issue Dt:
|
01/12/1999
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Application #:
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08695266
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Filing Dt:
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08/09/1996
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Title:
|
PARALLEL PROCESSING COMPUTER SYSTEM HAVING SHARED COHERENT MEMORY AND INTERCONNECTIONS UTILIZING SEPARATE UNIDIRECTIONAL REQUEST AND RESPONSE LINES FOR DIRECT COMMUNICATION OR USING CROSSBAR SWITCHING DEVICE
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Patent #:
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|
Issue Dt:
|
07/15/1997
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Application #:
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08705023
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Filing Dt:
|
08/29/1996
|
|
Title:
|
APPARATUS, SYSTEMS AND METHODS FOR IMPROVING DATA CACHE HIT RATES
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|
