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Patent Assignment Details
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Reel/Frame:015334/0772   Pages: 18
Recorded: 05/24/2004
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 371
Page 3 of 4
Pages: 1 2 3 4
1
Patent #:
Issue Dt:
04/17/2001
Application #:
09192019
Filing Dt:
11/11/1998
Title:
SHALLOW TRENCH ISOLATION METHOD OF A SEMICONDUCTOR WAFER
2
Patent #:
Issue Dt:
04/02/2002
Application #:
09198307
Filing Dt:
11/23/1998
Title:
METHOD FOR EVENLY IMMERSING A WAFER IN A SOLUTION
3
Patent #:
Issue Dt:
10/17/2000
Application #:
09198308
Filing Dt:
11/23/1998
Title:
METHOD FOR PREVENTING CORROSION OF A METALLIC LAYER OF A SEMICONDUCTOR CHIP
4
Patent #:
Issue Dt:
05/23/2000
Application #:
09198309
Filing Dt:
11/23/1998
Title:
METHOD FOR ENLARGING SURFACE AREA OF A PLURALITY OF HEMI-SPHERICAL GRAINS ON THE SURFACE OF A SEMICONDUCTOR CHIP
5
Patent #:
Issue Dt:
10/03/2000
Application #:
09213761
Filing Dt:
12/17/1998
Title:
CURRENT SENSING DIFFERENTIAL AMPLIFIER WITH HIGH REJECTION OF POWER SUPPLY VARIATIONS AND METHOD FOR AN INTEGRATED CIRCUIT MEMORY DEVICE
6
Patent #:
Issue Dt:
11/28/2000
Application #:
09217009
Filing Dt:
12/21/1998
Title:
IC LAYOUT STRUCTURE FOR MOSFET HAVING NARROW AND SHORT CHANNEL
7
Patent #:
Issue Dt:
02/20/2001
Application #:
09231707
Filing Dt:
01/13/1999
Title:
METHOD FOR MANUFACTURING THE STORAGE NODE OF A CAPACITOR ON A SEMICONDUCTOR WAFER
8
Patent #:
Issue Dt:
11/14/2000
Application #:
09236577
Filing Dt:
01/26/1999
Title:
METHOD OF LPCVD SILICONNITRIDE DEPOSITION
9
Patent #:
Issue Dt:
08/14/2001
Application #:
09239457
Filing Dt:
01/28/1999
Title:
GLOBAL PLANARIZATION METHOD FOR INTER-LAYER-DIELECTRIC AND INTER-METAL DIELECTRIC
10
Patent #:
Issue Dt:
06/13/2000
Application #:
09250952
Filing Dt:
02/16/1999
Title:
APPARATUS FOR PREPARING ULTRA-THIN SPECIMEN
11
Patent #:
Issue Dt:
05/22/2001
Application #:
09252489
Filing Dt:
02/18/1999
Title:
WAFER-FETCHING SENSING DEVICE FOR WAFER STORAGE APPARATUS
12
Patent #:
Issue Dt:
06/27/2000
Application #:
09252940
Filing Dt:
02/19/1999
Title:
METHOD FOR ESTIMATING THE THICKNESS OF LAYER COATED ON WAFER
13
Patent #:
Issue Dt:
10/09/2001
Application #:
09262065
Filing Dt:
03/04/1999
Title:
CONNECTING STRUCTURE BETWEEN FLUID CHANNEL
14
Patent #:
Issue Dt:
12/18/2001
Application #:
09264210
Filing Dt:
03/05/1999
Title:
MEMORY CELL WITH BUILT IN ERASURE FEATURE
15
Patent #:
Issue Dt:
07/03/2001
Application #:
09264600
Filing Dt:
03/08/1999
Title:
METHOD OF REMOVING A POLYSILICON BUFFER USING AN ETCHING SELECTIVITY SOLUTION
16
Patent #:
Issue Dt:
06/05/2001
Application #:
09265056
Filing Dt:
03/09/1999
Title:
CLEANING APPARATUS FOR MAINTAINING SEMICONDUCTOR EQUIPMENT
17
Patent #:
Issue Dt:
12/10/2002
Application #:
09265962
Filing Dt:
03/11/1999
Title:
MONITOR METHOD FOR QUALITY OF METAL ARC (ANTIREFLECTION COATING) LAYER
18
Patent #:
Issue Dt:
05/30/2000
Application #:
09265975
Filing Dt:
03/11/1999
Title:
METHOD FOR PROLONGING LIFE TIME OF A PLASMA ETCHING CHAMBER
19
Patent #:
Issue Dt:
06/05/2001
Application #:
09266285
Filing Dt:
03/11/1999
Title:
NEW POLY SPACER SPLIT GATE CELL WITH EXTREMELY SMALL CELL SIZE
20
Patent #:
Issue Dt:
09/18/2001
Application #:
09276865
Filing Dt:
03/26/1999
Title:
INSULATING APPARATUS FOR A CONDUCTIVE LINE
21
Patent #:
Issue Dt:
10/09/2001
Application #:
09277375
Filing Dt:
03/29/1999
Title:
SILICON ETCHING PROCESS
22
Patent #:
Issue Dt:
02/01/2000
Application #:
09281944
Filing Dt:
03/31/1999
Title:
HEIGHT GAUGE DEVICE FOR WAFER
23
Patent #:
Issue Dt:
09/05/2000
Application #:
09285454
Filing Dt:
04/02/1999
Title:
GAS RING APPARATUS FOR SEMICONDUCTOR ETCHING
24
Patent #:
Issue Dt:
08/14/2001
Application #:
09286287
Filing Dt:
04/06/1999
Title:
METHOD TO REDUCE THE PARTICLES IN LOAD- L0CK CHAMBER
25
Patent #:
Issue Dt:
07/17/2001
Application #:
09287440
Filing Dt:
04/07/1999
Title:
METHOD FOR FORMING A HEMISPHERICAL-GRAIN POLYSILICON
26
Patent #:
Issue Dt:
09/12/2000
Application #:
09296520
Filing Dt:
04/22/1999
Title:
CHEMICAL MECHANICAL POLISHING METHOD WITH IN-LINE THICKNESS DETECTION
27
Patent #:
Issue Dt:
03/14/2000
Application #:
09298868
Filing Dt:
04/26/1999
Title:
METHOD FOR FORMING A DEEP TRENCH CAPACITOR OF A DRAM CELL
28
Patent #:
Issue Dt:
06/12/2001
Application #:
09300432
Filing Dt:
04/28/1999
Title:
SOG DISPENSING SYSTEM AND ITS CONTROLLING SEQUENCES
29
Patent #:
Issue Dt:
10/10/2000
Application #:
09303598
Filing Dt:
05/03/1999
Title:
ION SOURCE CHAMBER OF A HIGH ENERGY IMPLANTER WITH A FILTERING DEVICE
30
Patent #:
Issue Dt:
06/12/2001
Application #:
09304013
Filing Dt:
04/30/1999
Title:
METHOD OF REMOVING POLYSILICON RESIDUAL IN A LOCOS ISOLATION PROCESS USING AN ETCHING SELECTIVITY SOLUTION
31
Patent #:
Issue Dt:
03/19/2002
Application #:
09305292
Filing Dt:
05/05/1999
Title:
METHOD OF FABRICATING AN OXIDE/NITRIDE MULTILAYER STRUCTURE FOR IC MANUFACTURE
32
Patent #:
Issue Dt:
04/23/2002
Application #:
09305524
Filing Dt:
05/05/1999
Title:
METHOD OF IN SITU REACTIVE GAS PLASMA TREATMENT
33
Patent #:
Issue Dt:
06/05/2001
Application #:
09306378
Filing Dt:
05/06/1999
Title:
METHOD FOR FORMING A DEEP TRENCH CAPACITOR OF A DRAM CELL
34
Patent #:
Issue Dt:
04/02/2002
Application #:
09310031
Filing Dt:
05/11/1999
Title:
METHOD FOR MAKING A CONCAVE BOTTOM OXIDE WITHIN A TRENCH
35
Patent #:
Issue Dt:
10/03/2000
Application #:
09310150
Filing Dt:
05/12/1999
Title:
MONITOR METHOD AND APPARATUS FOR OVERLAY ALIGNMENT OF A STEPPER
36
Patent #:
Issue Dt:
11/21/2000
Application #:
09313129
Filing Dt:
05/17/1999
Title:
METHOD FOR FABRICATING A TRENCH ISOLATION
37
Patent #:
Issue Dt:
02/15/2000
Application #:
09313668
Filing Dt:
05/18/1999
Title:
METOHD OF FORMING A TRENCH CAPACITOR WITHY A SACRIFICIAL SILICON NITR
38
Patent #:
Issue Dt:
08/07/2001
Application #:
09314154
Filing Dt:
05/19/1999
Title:
METHOD OF FORMING A TRENCH CAPACITOR
39
Patent #:
Issue Dt:
06/06/2000
Application #:
09323746
Filing Dt:
06/01/1999
Title:
METHOD TO PREVENT THE FORMATION OF A THINNER PORTION OF INSULATING LAYER AT THE JUNCTION BETWEEN THE SIDE WALLS AND THE BOTTOM INSULATOR
40
Patent #:
Issue Dt:
06/05/2001
Application #:
09325915
Filing Dt:
06/04/1999
Title:
METHOD FOR PREVENTING FILM DEPOSITED ON SEMICONDUCTOR WAFER FROM CRACKING
41
Patent #:
Issue Dt:
07/24/2001
Application #:
09326096
Filing Dt:
06/04/1999
Title:
METHOD FOR DETERMINING CRACK LIMIT OF FILM DEPOSITED ON SEMICONDUCTOR WAFER
42
Patent #:
Issue Dt:
02/13/2001
Application #:
09327491
Filing Dt:
06/08/1999
Title:
APPARATUS FOR EXTRACTING TEM SPECIMENS OF SEMICONDUCTOR DEVICES
43
Patent #:
Issue Dt:
06/12/2001
Application #:
09332125
Filing Dt:
06/14/1999
Title:
ION IMPLATATION PROCESS FOR FORMING CONTACT REGIONS IN SEMICONDUCTOR MATERIALS
44
Patent #:
Issue Dt:
03/20/2001
Application #:
09337982
Filing Dt:
06/22/1999
Title:
MODIFIED POLY-BUFFERED ISOLATION
45
Patent #:
Issue Dt:
08/08/2000
Application #:
09340404
Filing Dt:
06/28/1999
Title:
CONTROL DEVICE FOR MANUFACTURING A CHEMICAL MECHANICAL POLISHING MACHINE IN A WET MODE
46
Patent #:
Issue Dt:
12/25/2001
Application #:
09346732
Filing Dt:
07/02/1999
Title:
MARGIN INSPECTOR FOR IC WAFERS
47
Patent #:
Issue Dt:
06/27/2000
Application #:
09351183
Filing Dt:
07/12/1999
Title:
METHOD FOR FORMING A TRENCH POWER METAL-OXIDE SEMICONDUCTOR TRANSISTOR
48
Patent #:
Issue Dt:
01/09/2001
Application #:
09352411
Filing Dt:
07/14/1999
Title:
METHOD FOR FORMING RUGGED POLYSILICON CAPACITOR
49
Patent #:
Issue Dt:
02/06/2001
Application #:
09368628
Filing Dt:
08/05/1999
Title:
RADIO CONTROL ALARM DEVICE
50
Patent #:
Issue Dt:
07/30/2002
Application #:
09369265
Filing Dt:
08/06/1999
Title:
METHOD FOR ETCHING PASSIVATION LAYERS AND ANTIREFLECTIVE LAYER ON A SUBSTRATE
51
Patent #:
Issue Dt:
07/24/2001
Application #:
09369266
Filing Dt:
08/06/1999
Title:
METHOD FOR FABRICATING A CONCAVE BOTTOM OXIDE IN A TRENCH
52
Patent #:
Issue Dt:
10/03/2000
Application #:
09371378
Filing Dt:
08/10/1999
Title:
METHOD FOR FABRICATING MOSFET HAVING INCREASED EFFECTIVE GATE LENGTH
53
Patent #:
Issue Dt:
07/17/2001
Application #:
09373191
Filing Dt:
08/12/1999
Title:
METHOD FOR IMPROVING TRENCH ISOLATION
54
Patent #:
Issue Dt:
06/12/2001
Application #:
09375574
Filing Dt:
08/17/1999
Title:
PATTERNED MASK AND A DEEP TRENCH CAPACITOR FORMED THEREBY
55
Patent #:
Issue Dt:
11/07/2000
Application #:
09375638
Filing Dt:
08/17/1999
Title:
PROCESS AND STRUCTURE FOR INCREASING CAPACITANCE OF STACK CAPACITOR
56
Patent #:
Issue Dt:
01/30/2001
Application #:
09376464
Filing Dt:
08/18/1999
Title:
TRENCH NON-VOLATILE MEMORY CELL
57
Patent #:
Issue Dt:
11/27/2001
Application #:
09383373
Filing Dt:
08/26/1999
Title:
SINGLE POLY NON-VOLATILE MEMORY STRUCTURE AND ITS FABRICATING METHOD
58
Patent #:
Issue Dt:
09/26/2000
Application #:
09383374
Filing Dt:
08/26/1999
Title:
METHOD OF MANUFACTURING MOSFET DEVICES
59
Patent #:
Issue Dt:
07/18/2000
Application #:
09385382
Filing Dt:
08/30/1999
Title:
METHOD FOR PREVENTING BUBBLE DEFECTS IN BPSG FILM
60
Patent #:
Issue Dt:
02/12/2002
Application #:
09388929
Filing Dt:
09/02/1999
Title:
METHOD FOR EVALUATION OF METAL IMPURITY IN LITHOGRAPHIC MATERIALS
61
Patent #:
Issue Dt:
05/14/2002
Application #:
09390319
Filing Dt:
09/07/1999
Title:
WAFER LOAD/UNLOAD APPARATUS FOR E-GUN EVAPORATION PROCESS.
62
Patent #:
Issue Dt:
05/22/2001
Application #:
09400177
Filing Dt:
09/21/1999
Title:
TYPE OF HIGH DENSITY VERTICAL MASK ROM CELL
63
Patent #:
Issue Dt:
10/16/2001
Application #:
09400178
Filing Dt:
09/21/1999
Title:
NEW TYPE OF TRENCH MASK ROM CELL
64
Patent #:
Issue Dt:
08/14/2001
Application #:
09400179
Filing Dt:
09/21/1999
Title:
PIPING SYSTEM FOR ETCH EQUIPMENT
65
Patent #:
Issue Dt:
12/04/2001
Application #:
09400195
Filing Dt:
09/21/1999
Title:
SLEEVE FOR AN ADAPTER FLANGE OF THE GASONICS L3510 ETCHER
66
Patent #:
Issue Dt:
04/17/2001
Application #:
09406556
Filing Dt:
09/27/1999
Title:
PROCESS FOR FORMING SELF-ALIGNED CONTACT OF SEMICONDUCTOR DEVICE
67
Patent #:
Issue Dt:
11/14/2000
Application #:
09407268
Filing Dt:
09/29/1999
Title:
METHOD FOR FORMING SELF-ALIGNED CONTACT HOLE
68
Patent #:
Issue Dt:
07/30/2002
Application #:
09430895
Filing Dt:
11/01/1999
Title:
METHOD FOR PROTECTING A SPECIFIC REGION IN A SAMPLE APPLIED IN PREPARING AN ULTRA-THIN SPECIMEN
69
Patent #:
Issue Dt:
05/14/2002
Application #:
09430945
Filing Dt:
11/01/1999
Title:
METHOD FOR DISTINGUISHING A SPECIFIC REGION IN A SAMPLE TO BE OBSERVED BY A MICROSCOPE
70
Patent #:
Issue Dt:
03/06/2001
Application #:
09443945
Filing Dt:
11/19/1999
Title:
DIVOT FREE SHALLOW TRENCH ISOLATION PROCESS
71
Patent #:
Issue Dt:
02/06/2001
Application #:
09444988
Filing Dt:
11/23/1999
Title:
SELF-ALIGNED CONTACT FOR TRENCH DMOS TRANSISTORS
72
Patent #:
Issue Dt:
11/21/2000
Application #:
09455359
Filing Dt:
12/06/1999
Title:
SLURRY NOZZLE
73
Patent #:
Issue Dt:
05/08/2001
Application #:
09455924
Filing Dt:
12/07/1999
Title:
ASHING PROCESS BY ADJUSTING ETCHING ENDPOINT AND ORDERLY STEPPED POSITIONING SILICON WAFER
74
Patent #:
Issue Dt:
02/12/2002
Application #:
09459609
Filing Dt:
12/13/1999
Title:
DUAL DAMASCENE PROCESS
75
Patent #:
Issue Dt:
07/02/2002
Application #:
09460081
Filing Dt:
12/14/1999
Title:
EPROM CELL HAVING A GATE STRUCTURE WITH DUAL SIDE-WALL SPACERS OF DIFFERENTIAL COMPOSITION
76
Patent #:
Issue Dt:
11/21/2000
Application #:
09467086
Filing Dt:
12/10/1999
Title:
METHOD FOR FABRICATING MOS TRANSISTOR HAVING RAISED SOURCE AND DRAIN
77
Patent #:
Issue Dt:
01/01/2002
Application #:
09467877
Filing Dt:
12/21/1999
Title:
INSPECTION DEVICE FOR EXAMINING A PIECE OF APERTURE GRAPHITE OF AN EXTRACTION ELECTRODE
78
Patent #:
Issue Dt:
11/20/2001
Application #:
09478125
Filing Dt:
01/05/2000
Title:
Method for fabricating VLSI devices having trench isolation regions
79
Patent #:
Issue Dt:
05/14/2002
Application #:
09479535
Filing Dt:
01/07/2000
Title:
PLATE-TILTING APPARATUS
80
Patent #:
Issue Dt:
03/19/2002
Application #:
09483130
Filing Dt:
01/14/2000
Title:
METHOD FOR REWORKING PHOTORESIST
81
Patent #:
Issue Dt:
02/20/2001
Application #:
09487661
Filing Dt:
01/19/2000
Title:
Method for Planarizing A Polycrystalline Silicon Layer Deposited on a Trench
82
Patent #:
Issue Dt:
10/15/2002
Application #:
09488847
Filing Dt:
01/21/2000
Title:
METHOD FOR STABILIZING SEMICONDUCTOR DEGAS TEMPERATURE
83
Patent #:
Issue Dt:
11/27/2001
Application #:
09491405
Filing Dt:
01/26/2000
Title:
Conditioner assembly and a conditioner back support for a chemical mechanical polishing apparatus
84
Patent #:
Issue Dt:
02/27/2001
Application #:
09492726
Filing Dt:
01/27/2000
Title:
Dual slope sense clock generator
85
Patent #:
Issue Dt:
04/16/2002
Application #:
09493299
Filing Dt:
01/28/2000
Title:
BURST OPERATIONS IN MEMORIES
86
Patent #:
Issue Dt:
05/08/2001
Application #:
09514455
Filing Dt:
02/25/2000
Title:
Mos transistors having raised source and drain
87
Patent #:
Issue Dt:
07/24/2001
Application #:
09516336
Filing Dt:
03/01/2000
Title:
Programmable latches that include non-volatile programmable elements
88
Patent #:
Issue Dt:
03/05/2002
Application #:
09519732
Filing Dt:
03/03/2000
Title:
Method for reducing nitride residue in a locos isolation area
89
Patent #:
Issue Dt:
05/13/2003
Application #:
09523064
Filing Dt:
03/10/2000
Title:
FLASH CELL DEVICE
90
Patent #:
Issue Dt:
02/20/2001
Application #:
09523590
Filing Dt:
03/10/2000
Title:
Memory burst operations in which address count bits are used as column address bits for one but not both of the odd and even columns selected in parallel
91
Patent #:
Issue Dt:
06/24/2003
Application #:
09524644
Filing Dt:
03/14/2000
Title:
ARBITRATION METHOD AND CIRCUIT FOR CONTROL OF INTEGRATED CIRCUIT DOUBLE DATA RATE (DDR) MEMORY DEVICE OUTPUT FIRST-IN, FIRST-OUT (FIFO) REGISTERS
92
Patent #:
Issue Dt:
07/02/2002
Application #:
09527048
Filing Dt:
03/16/2000
Title:
SYSTEM AND METHOD FOR SUPPORTING SEQUENTIAL BURST COUNTS IN DOUBLE DATA RATE (DDR) SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORIES (SDRAM)
93
Patent #:
Issue Dt:
04/09/2002
Application #:
09531233
Filing Dt:
03/21/2000
Title:
METHOD FOR DETECTING ORGANIC CONTAMINATION BY USING HEMISPHERICAL-GRAIN POLYSILICON LAYER
94
Patent #:
Issue Dt:
12/12/2000
Application #:
09531580
Filing Dt:
03/21/2000
Title:
Self-timed data amplifier and method for an integrated circuit memory device
95
Patent #:
Issue Dt:
09/04/2001
Application #:
09534699
Filing Dt:
03/24/2000
Title:
MOS transistors having dual gates and self-aligned interconnect contact windows
96
Patent #:
Issue Dt:
03/19/2002
Application #:
09541876
Filing Dt:
04/03/2000
Title:
System and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line
97
Patent #:
Issue Dt:
02/12/2002
Application #:
09542509
Filing Dt:
04/03/2000
Title:
Low power consumption integrated circuit delay locked loop and method for controlling the same
98
Patent #:
Issue Dt:
01/15/2002
Application #:
09542511
Filing Dt:
04/03/2000
Title:
System and method for eliminating pulse width variations in digital delay lines
99
Patent #:
Issue Dt:
06/26/2001
Application #:
09546800
Filing Dt:
04/11/2000
Title:
Method of fabricating a trench capacitor
100
Patent #:
Issue Dt:
09/03/2002
Application #:
09547384
Filing Dt:
04/11/2000
Title:
DYNAMIC DATA AMPLIFIER WITH BUILT-IN VOLTAGE LEVEL SHIFTING
Assignor
1
Exec Dt:
04/27/2004
Assignee
1
3F, NO.19, LI-HSIN ROAD
SCIENCE-BASED INDUSTRIAL PARK
HSIN-CHU CITY, TAIWAN
Correspondence name and address
MACPHERSON KWOK CHEN ET.AL.
MICHAEL SHENKER
1762 TECHNOLOGY DRIVE, SUITE 226
SAN JOSE, CA 95110

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