Total properties:
28
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Patent #:
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Issue Dt:
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04/22/2014
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Application #:
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13564071
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Filing Dt:
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08/01/2012
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Publication #:
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Pub Dt:
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08/08/2013
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Title:
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METHODS FOR PFET FABRICATION USING APM SOLUTIONS
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Patent #:
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Issue Dt:
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04/16/2019
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Application #:
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15444899
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Filing Dt:
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02/28/2017
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Publication #:
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Pub Dt:
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08/30/2018
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Title:
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METHODOLOGY FOR MODEL-BASED SELF-ALIGNED VIA AWARENESS IN OPTICAL PROXIMITY CORRECTION
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Patent #:
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Issue Dt:
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02/26/2019
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Application #:
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15456757
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Filing Dt:
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03/13/2017
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Publication #:
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Pub Dt:
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09/13/2018
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Title:
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SUBSTANTIALLY DEFECT-FREE POLYSILICON GATE ARRAYS
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15478377
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Filing Dt:
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04/04/2017
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Publication #:
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Pub Dt:
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10/04/2018
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Title:
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SRAF INSERTION WITH ARTIFICIAL NEURAL NETWORK
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Patent #:
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Issue Dt:
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09/03/2019
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Application #:
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15588984
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Filing Dt:
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05/08/2017
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Publication #:
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Pub Dt:
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11/08/2018
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Title:
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PREDICTION OF PROCESS-SENSITIVE GEOMETRIES WITH MACHINE LEARNING
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Patent #:
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Issue Dt:
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04/16/2019
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Application #:
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15597202
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Filing Dt:
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05/17/2017
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Publication #:
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Pub Dt:
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11/22/2018
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Title:
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PROBE CARD SUPPORT INSERT, CONTAINER, SYSTEM AND METHOD FOR STORING AND TRANSPORTING ONE OR MORE PROBE CARDS
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Patent #:
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Issue Dt:
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06/25/2019
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Application #:
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15597277
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Filing Dt:
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05/17/2017
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Publication #:
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Pub Dt:
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11/22/2018
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Title:
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DUMMY ASSIST FEATURES FOR PATTERN SUPPORT
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Patent #:
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Issue Dt:
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04/02/2019
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Application #:
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15602810
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Filing Dt:
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05/23/2017
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Publication #:
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Pub Dt:
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11/29/2018
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Title:
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MULTI-STAGE PATTERN RECOGNITION IN CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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10/01/2019
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Application #:
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15609621
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Filing Dt:
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05/31/2017
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Publication #:
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Pub Dt:
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12/06/2018
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Title:
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SHIELDED SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING SHIELDED SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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03/19/2019
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Application #:
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15617403
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Filing Dt:
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06/08/2017
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Publication #:
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Pub Dt:
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12/13/2018
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Title:
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MATCHING IC DESIGN PATTERNS USING WEIGHTED XOR DENSITY
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Patent #:
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Issue Dt:
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06/18/2019
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Application #:
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15622061
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Filing Dt:
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06/13/2017
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Publication #:
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Pub Dt:
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12/13/2018
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Title:
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METHODS, APPARATUS AND SYSTEM FOR THRESHOLD VOLTAGE CONTROL IN FINFET DEVICES
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Patent #:
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Issue Dt:
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07/16/2019
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Application #:
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15624764
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Filing Dt:
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06/16/2017
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Publication #:
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Pub Dt:
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12/20/2018
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Title:
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MODELING 3D PHYSICAL CONNECTIVITY INTO PLANAR 2D DOMAIN TO IDENTIFY VIA REDUNDANCY
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Patent #:
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Issue Dt:
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05/21/2019
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Application #:
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15652594
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Filing Dt:
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07/18/2017
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Publication #:
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Pub Dt:
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01/24/2019
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Title:
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INTERCONNECT STRUCTURES FOR A SECURITY APPLICATION
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15653638
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Filing Dt:
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07/19/2017
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Publication #:
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Pub Dt:
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01/24/2019
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Title:
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VIA AND SKIP VIA STRUCTURES
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Patent #:
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Issue Dt:
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08/06/2019
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Application #:
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15662419
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Filing Dt:
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07/28/2017
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Publication #:
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Pub Dt:
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01/31/2019
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Title:
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IC LAYOUT POST-DECOMPOSITION MASK ALLOCATION OPTIMIZATION
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Patent #:
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Issue Dt:
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04/30/2019
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Application #:
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15665974
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Filing Dt:
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08/01/2017
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Publication #:
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Pub Dt:
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02/07/2019
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Title:
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SPLIT PROBE PAD STRUCTURE AND METHOD
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Patent #:
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Issue Dt:
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06/04/2019
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Application #:
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15670158
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Filing Dt:
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08/07/2017
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Publication #:
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Pub Dt:
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02/07/2019
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Title:
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ALIGNMENT KEY DESIGN RULE CHECK FOR CORRECT PLACEMENT OF ABUTTING CELLS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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15693651
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Filing Dt:
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09/01/2017
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Title:
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SELF-ALIGNED METAL WIRE ON CONTACT STRUCTURE AND METHOD FOR FORMING SAME
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Patent #:
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Issue Dt:
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04/30/2019
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Application #:
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15709730
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Filing Dt:
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09/20/2017
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Publication #:
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Pub Dt:
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03/21/2019
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Title:
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METHODS FOR FORMING FINS
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Patent #:
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Issue Dt:
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09/03/2019
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Application #:
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15719680
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Filing Dt:
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09/29/2017
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Publication #:
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Pub Dt:
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04/04/2019
| | | | |
Title:
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GENERATING RISK INVENTORY AND COMMON PROCESS WINDOW FOR ADJUSTMENT OF MANUFACTURING TOOL
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Patent #:
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Issue Dt:
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08/20/2019
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Application #:
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15720182
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Filing Dt:
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09/29/2017
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Publication #:
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Pub Dt:
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04/04/2019
| | | | |
Title:
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GEOMETRY VECTORIZATION FOR MASK PROCESS CORRECTION
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Patent #:
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Issue Dt:
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08/20/2019
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Application #:
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15730830
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Filing Dt:
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10/12/2017
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Publication #:
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Pub Dt:
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04/18/2019
| | | | |
Title:
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METHODOLOGY FOR POST-INTEGRATION AWARENESS IN OPTICAL PROXIMITY CORRECTION
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Patent #:
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Issue Dt:
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09/03/2019
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Application #:
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15805179
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Filing Dt:
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11/07/2017
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Publication #:
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Pub Dt:
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05/09/2019
| | | | |
Title:
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PELLICLE REPLACEMENT IN EUV MASK FLOW
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Patent #:
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Issue Dt:
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08/06/2019
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Application #:
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15829459
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Filing Dt:
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12/01/2017
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Publication #:
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Pub Dt:
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06/06/2019
| | | | |
Title:
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LOGIC LAYOUT WITH REDUCED AREA AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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03/12/2019
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Application #:
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15860231
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Filing Dt:
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01/02/2018
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Title:
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CUT-FIRST APPROACH WITH SELF-ALIGNMENT DURING LINE PATTERNING
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Patent #:
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Issue Dt:
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01/29/2019
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Application #:
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15913547
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Filing Dt:
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03/06/2018
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Title:
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SEMICONDUCTOR DEVICES WITH ROBUST LOW-K SIDEWALL SPACERS AND METHOD FOR PRODUCING THE SAME
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Patent #:
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Issue Dt:
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06/18/2019
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Application #:
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16159877
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Filing Dt:
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10/15/2018
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Title:
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FinFET CUT ISOLATION OPENING REVISION TO COMPENSATE FOR OVERLAY INACCURACY
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Patent #:
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Issue Dt:
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09/24/2019
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Application #:
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16398841
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Filing Dt:
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04/30/2019
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Title:
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FinFET CUT ISOLATION OPENING REVISION TO COMPENSATE FOR OVERLAY INACCURACY
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