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Patent Assignment Details
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Reel/Frame:012287/0780   Pages: 31
Recorded: 06/22/2001
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 72
1
Patent #:
Issue Dt:
02/16/1988
Application #:
06534035
Filing Dt:
09/20/1983
Title:
FET READ ONLY MEMORY CELL WITH WORD LINE AUGMENTED PRECHARGING OF THE BIT LINES
2
Patent #:
Issue Dt:
01/10/1989
Application #:
07023426
Filing Dt:
03/09/1987
Title:
HIGH DENSITY, HIGH PERFORMANCE, SINGLE EVENT UPSET IMMUNE DATA STORAGE CELL
3
Patent #:
Issue Dt:
11/07/1989
Application #:
07156626
Filing Dt:
02/17/1988
Title:
PARITY GENERATOR CIRCUIT AND METHOD
4
Patent #:
Issue Dt:
07/25/1989
Application #:
07176052
Filing Dt:
03/31/1988
Title:
SOFT ERROR RESISTANT DATA STORAGE CELLS
5
Patent #:
Issue Dt:
02/26/1991
Application #:
07414889
Filing Dt:
09/28/1989
Title:
ZERO STANDBY POWER, RADIATION HARDENED, MEMORY REDUNDANCY CIRCUIT
6
Patent #:
Issue Dt:
05/26/1992
Application #:
07598300
Filing Dt:
10/16/1990
Title:
CMOS OFF CHIP DRIVER FOR FAULT TOLERANT COLD SPARING
7
Patent #:
Issue Dt:
08/10/1993
Application #:
07829667
Filing Dt:
02/03/1992
Title:
SMALL CELL, LOW CONTACT ASSISTANCE RUGGED POWER FIELD EFFECT DEVICES AND METHOD OF FABRICATION
8
Patent #:
Issue Dt:
04/26/1994
Application #:
07876239
Filing Dt:
04/30/1992
Title:
DISTRIBUTED PROGRAMMABLE PRIORITY ARBITRATION
9
Patent #:
Issue Dt:
11/15/1994
Application #:
08004217
Filing Dt:
01/13/1993
Title:
FAST FOURIER TRANSFORM USING BALANCED COEFFICIENTS
10
Patent #:
Issue Dt:
05/24/1994
Application #:
08054992
Filing Dt:
04/30/1993
Title:
METHOD OF FORMING A FRONTSIDE CONTACT TO THE SILICON SUBSTRATE OF A SOI WAFER
11
Patent #:
Issue Dt:
10/25/1994
Application #:
08054994
Filing Dt:
04/30/1993
Title:
METHOD OF MAKING GATE OVERLAPPED LIGHTLY DOPED DRAIN FOR BURIED CHANNEL DEVICES
12
Patent #:
Issue Dt:
07/01/1997
Application #:
08131346
Filing Dt:
10/04/1993
Title:
POWER BUS DIGITAL COMMUNICATION SYSTEM
13
Patent #:
Issue Dt:
11/01/1994
Application #:
08142030
Filing Dt:
10/28/1993
Title:
METHOD TO RADIATION HARDEN THE BURIED OXIDE IN SILICON-ON-INSULATOR STRUCTURES
14
Patent #:
Issue Dt:
09/05/1995
Application #:
08212372
Filing Dt:
03/14/1994
Title:
SPARE SIGNAL LINE SWITCHING METHOD AND APPARATUS
15
Patent #:
Issue Dt:
06/18/1996
Application #:
08304639
Filing Dt:
09/12/1994
Title:
METHOD TO PREVENT LATCH-UP AND IMPROVE BREAKDOWN VOLTAGE IN SOI MOSFETS
16
Patent #:
Issue Dt:
10/10/1995
Application #:
08371718
Filing Dt:
01/12/1995
Title:
CURRENT OVERLOAD PROTECTION CIRCUIT
17
Patent #:
Issue Dt:
04/02/1996
Application #:
08382112
Filing Dt:
02/01/1995
Title:
SINGLE EVENT UPSET HARDENED CMOS LATCH CIRCUIT
18
Patent #:
Issue Dt:
04/02/1996
Application #:
08389993
Filing Dt:
02/17/1995
Title:
MAGNIFICATION CORRECTION FOR 1-X PROXIMITY X-RAY LITHOGRAPHY
19
Patent #:
Issue Dt:
06/11/1996
Application #:
08391798
Filing Dt:
02/21/1995
Title:
SINGLE EVENT UPSET IMMUNE REGISTER WITH FAST WRITE ACCESS
20
Patent #:
Issue Dt:
01/28/1997
Application #:
08559584
Filing Dt:
11/16/1995
Title:
EFFICIENT FAULT TOLERANT SWITCHING CIRCUIT FOR REDUNDANT D.C. POWER SUPPLIES
21
Patent #:
Issue Dt:
06/22/1999
Application #:
08660640
Filing Dt:
06/07/1996
Title:
ERROR DETECTION AND FAULT ISOLATION FOR LOCKSTEP PROCESSOR SYSTEMS
22
Patent #:
Issue Dt:
05/26/1998
Application #:
08663826
Filing Dt:
06/14/1996
Title:
HIGH ACCURACY FABRICATION OF X-RAY MASKS WITH OPTICAL AND E-BEAM LITHOGRAPHY
23
Patent #:
Issue Dt:
08/11/1998
Application #:
08716657
Filing Dt:
09/06/1996
Title:
X-RAY MASK PELLICLE
24
Patent #:
Issue Dt:
01/12/1999
Application #:
08728880
Filing Dt:
10/10/1996
Title:
PROCESS TO PERSONALIZE MASTER SLICE WAFERS AND FABRICATE HIGH DENSITY VLSI COMPONENTS WITH A SINGLE MASKING STEP
25
Patent #:
Issue Dt:
08/18/1998
Application #:
08733080
Filing Dt:
10/16/1996
Title:
FAULT TOLERANT MOSFET DRIVER
26
Patent #:
Issue Dt:
09/15/1998
Application #:
08740598
Filing Dt:
10/31/1996
Title:
LITHOGRAPHIC PATTERNING METHOD AND MASK SET THEREFOR WITH LIGHT FIELD TRIM MASK
27
Patent #:
Issue Dt:
03/07/2000
Application #:
08812183
Filing Dt:
03/06/1997
Title:
ELECTROSTATIC DISCHARGE PROTECTION FOR SILICON-ON-INSULATOR
28
Patent #:
Issue Dt:
05/04/1999
Application #:
08812184
Filing Dt:
03/06/1997
Title:
RING DOMAINS FOR BANDWIDTH SHARING
29
Patent #:
Issue Dt:
10/19/1999
Application #:
08837165
Filing Dt:
04/14/1997
Title:
SECURE DATA TRANSMISSION ON A TDM ISOCHRONOUS NETWORK
30
Patent #:
Issue Dt:
02/02/1999
Application #:
08884650
Filing Dt:
06/27/1997
Title:
DIGITAL MULTI-CHANNEL DEMULTIPLEXER/MULTIPLEX (MCD/M ARCHITECTURE).
31
Patent #:
Issue Dt:
02/13/2001
Application #:
08884675
Filing Dt:
06/27/1997
Title:
CONTROL AND TELEMETRY SIGNAL COMMUNICATION SYSTEM FOR GEOSTATIONARY SATELLITES
32
Patent #:
Issue Dt:
04/18/2000
Application #:
08989463
Filing Dt:
12/12/1997
Title:
REVERSIBLE KEYPAD AND DISPLAY FOR A TELEPHONE HANDSET
33
Patent #:
Issue Dt:
12/11/2001
Application #:
09007980
Filing Dt:
01/16/1998
Title:
INTEGRATED CIRCUIT PACKAGE AND METHOD INCREASING DENSITY OF I/O LEADS
34
Patent #:
Issue Dt:
10/03/2000
Application #:
09030902
Filing Dt:
02/26/1998
Title:
MULTI-CHANNEL OVERVOLTAGE PROTECTION CIRCUIT
35
Patent #:
Issue Dt:
07/18/2000
Application #:
09241313
Filing Dt:
02/01/1999
Title:
DIGITAL MULTI-CHANNEL DEMULTIPLEXER/MULTIPLEXER (MCD/M) ARCHITECTURE
36
Patent #:
Issue Dt:
04/02/2002
Application #:
09307126
Filing Dt:
05/07/1999
Title:
PATTERN DENSITY TAILORING FOR ETCHING OF ADVANCED LITHOGRAPHIC MASKS
37
Patent #:
Issue Dt:
01/02/2001
Application #:
09320207
Filing Dt:
05/26/1999
Title:
MEMORY DEVICE HAVING A CHIP SELECT SPEEDUP FEATURE AND ASSOCIATED METHODS
38
Patent #:
Issue Dt:
01/30/2001
Application #:
09320227
Filing Dt:
05/26/1999
Title:
MEMORY DEVICE HAVING REDUCED POWER REQUIREMENTS AND ASSOCIATED METHODS
39
Patent #:
Issue Dt:
04/24/2001
Application #:
09321565
Filing Dt:
05/28/1999
Title:
METHOD AND APPARATUS FOR EVALUATING A KNOWN GOOD DIE USING BOTH WIRE BOND AND FLIP-CHIP INTERCONNECTS
40
Patent #:
Issue Dt:
05/16/2000
Application #:
09325641
Filing Dt:
06/04/1999
Title:
ERROR DETECTION AND FAULT ISOLATION FOR LOCKSTEP PROCESSOR SYSTEMS
41
Patent #:
Issue Dt:
08/29/2000
Application #:
09325645
Filing Dt:
06/04/1999
Title:
RADIATION HARDENED SIX TRANSISTOR RANDOM ACCESS MEMORY AND MEMORY DEVICE
42
Patent #:
Issue Dt:
01/21/2003
Application #:
09384429
Filing Dt:
08/27/1999
Publication #:
Pub Dt:
05/09/2002
Title:
SATELLITE TELEPHONE HANDSET
43
Patent #:
Issue Dt:
09/04/2001
Application #:
09441941
Filing Dt:
11/17/1999
Title:
METHOD AND APPARATUS FOR HARDENING A STATIC RANDOM ACCESS MEMORY CELL FROM SINGLE EVENT UPSETS
44
Patent #:
Issue Dt:
03/27/2001
Application #:
09441942
Filing Dt:
11/17/1999
Title:
SINGLE EVENT UPSET (SEU) HARDENED STATIC RANDOM ACCESS MEMORY CELL
45
Patent #:
Issue Dt:
04/09/2002
Application #:
09449723
Filing Dt:
11/24/1999
Title:
SINGLE-EVENT UPSET HARDENED RECONFIGURABLE BI-STABLE CMOS LATCH
46
Patent #:
Issue Dt:
08/14/2001
Application #:
09480454
Filing Dt:
01/11/2000
Title:
ENHANCED SINGLE EVENT UPSET IMMUNE LATCH CIRCUIT
47
Patent #:
Issue Dt:
04/06/2004
Application #:
09491230
Filing Dt:
01/25/2000
Title:
METHOD FOR FABRICATING RESISTORS WITHIN SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES
48
Patent #:
Issue Dt:
04/06/2004
Application #:
09502062
Filing Dt:
02/10/2000
Title:
IN SITU PROXIMITY GAP MONITOR FOR LITHOGRAPHY
49
Patent #:
Issue Dt:
04/10/2001
Application #:
09553595
Filing Dt:
04/20/2000
Title:
Self-restoring single event upset (seu) hardened multiport memory cell
50
Patent #:
Issue Dt:
09/24/2002
Application #:
09559659
Filing Dt:
04/28/2000
Title:
METHOD AND APPARATUS FOR A SINGLE EVENT UPSET (SEU) TOLERANT CLOCK SPLITTER
51
Patent #:
Issue Dt:
09/30/2003
Application #:
09559660
Filing Dt:
04/28/2000
Title:
METHOD AND APPARATUS FOR A SCANNABLE HYBRID FLIP FLOP
52
Patent #:
Issue Dt:
03/26/2002
Application #:
09559661
Filing Dt:
04/28/2000
Title:
Method and apparatus for a single even upset (SEU) tolerant clock splitter
53
Patent #:
Issue Dt:
07/09/2002
Application #:
09563197
Filing Dt:
05/02/2000
Title:
METHOD AND APPARATUS FOR A VOLTAGE RESPONSIVE RESET FOR EEPROM
54
Patent #:
Issue Dt:
04/26/2005
Application #:
09570050
Filing Dt:
05/12/2000
Title:
DISTRIBUTED DETERMINATION OF EXPLICIT RATE IN AN ATM COMMUNICATION SYSTEM
55
Patent #:
Issue Dt:
10/09/2001
Application #:
09570064
Filing Dt:
05/12/2000
Title:
Self-equalized low poer precharge sense amp for high speed srams
56
Patent #:
Issue Dt:
08/28/2001
Application #:
09589732
Filing Dt:
06/08/2000
Title:
Multiplexor having a single event upset (SEU) immune data keeper circuit
57
Patent #:
Issue Dt:
09/21/2004
Application #:
09590805
Filing Dt:
06/09/2000
Title:
INCREASING THE SUSCEPTABILITY OF AN INTEGRATED CIRCUIT TO IONIZING RADIATION
58
Patent #:
Issue Dt:
08/27/2002
Application #:
09590806
Filing Dt:
06/09/2000
Title:
SEMICONDUCTOR DEVICE AND CIRCUIT HAVING LOW TOLERANCE TO IONIZING RADIATION
59
Patent #:
Issue Dt:
05/17/2005
Application #:
09591731
Filing Dt:
06/12/2000
Title:
SYSTEM AND METHOD OF PROVIDING A SPREAD SPECTRUM PULSE WIDTH MODULATOR CLOCK
60
Patent #:
Issue Dt:
05/01/2001
Application #:
09591958
Filing Dt:
06/12/2000
Title:
Circuit for limiting inrush current through a transistor
61
Patent #:
Issue Dt:
12/04/2001
Application #:
09592403
Filing Dt:
06/13/2000
Title:
Process for production of 1, 3-DI (2-p-hydroxyphenyl-2-propyl) benzene
62
Patent #:
Issue Dt:
03/25/2003
Application #:
09597229
Filing Dt:
06/20/2000
Title:
TOOL SUITE FOR THE RAPID DEVELOPMENT OF ADVANCED STANDARD CELL LIBRARIES
63
Patent #:
Issue Dt:
08/06/2002
Application #:
09598681
Filing Dt:
06/21/2000
Title:
LOW -POWER CMOS DEVICE AND LOGIC GATES/CIRCUITS THEREWITH
64
Patent #:
Issue Dt:
02/24/2004
Application #:
09624247
Filing Dt:
07/24/2000
Title:
METHOD FOR TESTING OF KNOWN GOOD DIE
65
Patent #:
Issue Dt:
02/26/2002
Application #:
09625641
Filing Dt:
07/25/2000
Title:
Digital multi-channel demultiplexer/multiplexer (MCD/M) architecture
66
Patent #:
Issue Dt:
06/04/2002
Application #:
09630216
Filing Dt:
08/01/2000
Title:
RADIATION HARDENED SILICON-ON-INSULATOR (SOI) TRANSISTOR HAVING A BODY CONTACT
67
Patent #:
Issue Dt:
10/28/2003
Application #:
09636125
Filing Dt:
08/10/2000
Title:
REDUNDANT OSCILLATOR AND METHOD FOR GENERATING A REGULATED SIGNAL
68
Patent #:
Issue Dt:
07/10/2001
Application #:
09651155
Filing Dt:
08/30/2000
Title:
Single event upset (SEU) hardened static random access memory cell
69
Patent #:
Issue Dt:
05/21/2002
Application #:
09651156
Filing Dt:
08/30/2000
Title:
CIRCUIT FOR FILTERING SINGLE EVENT EFFECT (SEE) INDUCED GLITCHES
70
Patent #:
Issue Dt:
09/10/2002
Application #:
09667040
Filing Dt:
09/21/2000
Title:
SINGLE EVENT UPSET IMMUNE OSCILLATOR CIRCUIT
71
Patent #:
Issue Dt:
09/28/1999
Application #:
29069642
Filing Dt:
03/27/1997
Title:
DUAL MODE TELEPHONE HANDSET
72
Patent #:
Issue Dt:
Application #:
94208079
Filing Dt:
Title:
Assignor
1
Exec Dt:
11/27/2000
Assignee
1
P.O. BOX 868, NHQ1-719
NASHUA, NEW HAMPSHIRE 03061
Correspondence name and address
SWIDLER BERLIN SHEREFF FRIEDMAN, LLP
EDWARD A. PENNINGTON
3000 K STREET, N.W.
SUITE 300
WASHINGTON, D.C. 20007-5116

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