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Reel/Frame:020326/0781   Pages: 4
Recorded: 01/07/2008
Attorney Dkt #:QIM 2007 VJ 32715 US
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
11874768
Filing Dt:
10/18/2007
Publication #:
Pub Dt:
04/23/2009
Title:
Method of Testing an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Integrated Circuit
Assignor
1
Exec Dt:
11/16/2007
Assignees
1
GUSTAV-HEINEMANN-RING 212
MUNICH, GERMANY 81739
2
224 BLD. JOHN KENNEDY
CORBEIL ESSONNES CEDEX, FRANCE ZIP 31 P 91105
Correspondence name and address
SLATER & MATSIL, L.L.P
17950 PRESTON RD.
SUITE 1000
DALLAS, TX 75252

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