Patent Assignment Details
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Reel/Frame: | 023413/0782 | |
| Pages: | 9 |
| | Recorded: | 10/23/2009 | | |
Attorney Dkt #: | SILIP114US |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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07/17/2012
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Application #:
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12504308
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Filing Dt:
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07/16/2009
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Publication #:
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Pub Dt:
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01/20/2011
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Title:
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METHOD AND APPARTUS FOR SUB-ASSEMBLY ERROR DETECTION IN HIGH VOLTAGE ANALOG CIRCUITS AND PINS
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Assignee
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3300 CENTRAL EXPRESSWAY |
SANTA CLARA, CALIFORNIA 95051 |
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Correspondence name and address
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VINAY JOSHI
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127 PUBLIC SQUARE
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57TH FLOOR, KEY TOWER
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CLEVELAND, OH 44114
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