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Total properties:
32
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10794782
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Filing Dt:
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03/03/2004
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Publication #:
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Pub Dt:
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09/08/2005
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Title:
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DATA SORTING IN MEMORIES
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10816727
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Filing Dt:
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04/02/2004
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Publication #:
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Pub Dt:
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10/06/2005
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Title:
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MULTISTAGE PARALLEL-TO-SERIAL CONVERSION OF READ DATA IN MEMORIES, WITH THE FIRST SERIAL BIT SKIPPING AT LEAST ONE STAGE
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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11092506
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Filing Dt:
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03/29/2005
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Publication #:
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Pub Dt:
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10/05/2006
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Title:
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HIGH-SPEED, LOW-POWER INPUT BUFFER FOR INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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11257610
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Filing Dt:
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10/25/2005
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Publication #:
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Pub Dt:
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04/26/2007
| | | | |
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Title:
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WIDE WINDOW CLOCK SCHEME FOR LOADING OUTPUT FIFO REGISTERS
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Patent #:
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Issue Dt:
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06/17/2008
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Application #:
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11365013
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Filing Dt:
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03/01/2006
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Publication #:
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Pub Dt:
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09/06/2007
| | | | |
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Title:
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REDUCING NITROGEN CONCENTRATION WITH IN-SITU STEAM GENERATION
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Patent #:
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Issue Dt:
|
04/08/2008
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Application #:
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11514743
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Filing Dt:
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08/31/2006
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Title:
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FABRICATION OF SEMICONDUCTOR DEVICE EXHIBITING REDUCED DIELECTRIC LOSS IN ISOLATION TRENCHES
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Patent #:
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Issue Dt:
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04/07/2009
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Application #:
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11559791
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Filing Dt:
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11/14/2006
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Publication #:
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Pub Dt:
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05/15/2008
| | | | |
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Title:
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REFRESH PERIOD ADJUSTMENT TECHNIQUE FOR DYNAMIC RANDOM ACCESS MEMORIES (DRAM) AND INTEGRATED CIRCUIT DEVICES INCORPORATING EMBEDDED DRAM
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Patent #:
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Issue Dt:
|
04/14/2009
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Application #:
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11671383
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Filing Dt:
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02/05/2007
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Publication #:
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Pub Dt:
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08/07/2008
| | | | |
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Title:
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CIRCUIT AND TECHNIQUE FOR ADJUSTING AND ACCURATELY CONTROLLING CLOCK DUTY CYCLES IN INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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09/01/2009
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Application #:
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11687605
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Filing Dt:
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03/16/2007
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Publication #:
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Pub Dt:
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08/02/2007
| | | | |
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Title:
|
HIGH-SPEED, LOW-POWER INPUT BUFFER FOR INTEGRATED CIRCUIT DEVICES
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|
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Patent #:
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Issue Dt:
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11/18/2008
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Application #:
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11739482
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Filing Dt:
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04/24/2007
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Publication #:
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Pub Dt:
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10/30/2008
| | | | |
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Title:
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INTEGRATED CIRCUITS WITH SUBSTRATE PROTRUSIONS, INCLUDING (BUT NOT LIMITED TO) FLOATING GATE MEMORIES
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Patent #:
|
|
Issue Dt:
|
01/06/2009
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Application #:
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11745911
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Filing Dt:
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05/08/2007
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Publication #:
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Pub Dt:
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11/13/2008
| | | | |
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Title:
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USE OF MULTIPLE VOLTAGE CONTROLLED DELAY LINES FOR PRECISE ALIGNMENT AND DUTY CYCLE CONTROL OF THE DATA OUTPUT OF A DDR MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/04/2009
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Application #:
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11767329
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Filing Dt:
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06/22/2007
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Publication #:
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Pub Dt:
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12/25/2008
| | | | |
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Title:
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AUTOMATIC DUTY CYCLE CORRECTION CIRCUIT WITH PROGRAMMABLE DUTY CYCLE TARGET
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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11872477
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Filing Dt:
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10/15/2007
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Publication #:
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Pub Dt:
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04/16/2009
| | | | |
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Title:
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NON-VOLATILE MEMORY DEVICES WITH CHARGE STORAGE REGIONS
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Patent #:
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|
Issue Dt:
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11/09/2010
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Application #:
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11943931
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Filing Dt:
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11/21/2007
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Publication #:
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Pub Dt:
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05/21/2009
| | | | |
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Title:
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METHODS FOR INSPECTING AND OPTIONALLY REWORKING SUMMED PHOTOLITHOGRAPHY PATTERNS RESULTING FROM PLURALLY-OVERLAID PATTERNING STEPS DURING MASS PRODUCTION OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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02/15/2011
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Application #:
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11955352
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Filing Dt:
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12/12/2007
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Publication #:
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Pub Dt:
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06/18/2009
| | | | |
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Title:
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N-BIT SHIFT REGISTER CONTROLLER
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|
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Patent #:
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|
Issue Dt:
|
10/19/2010
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Application #:
|
11961183
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Filing Dt:
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12/20/2007
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Publication #:
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Pub Dt:
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06/25/2009
| | | | |
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Title:
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NONVOLATILE MEMORIES WITH LATERALLY RECESSED CHARGE-TRAPPING DIELECTRIC
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|
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Patent #:
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|
Issue Dt:
|
02/15/2011
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Application #:
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12021209
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Filing Dt:
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01/28/2008
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Publication #:
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Pub Dt:
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07/30/2009
| | | | |
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Title:
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USING DIFFERENTIAL DATA STROBES IN NON-DIFFERENTIAL MODE TO ENHANCE DATA CAPTURE WINDOW
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|
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Patent #:
|
|
Issue Dt:
|
03/29/2011
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Application #:
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12044664
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Filing Dt:
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03/07/2008
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Publication #:
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Pub Dt:
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09/10/2009
| | | | |
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Title:
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TWIN CELL ARCHITECTURE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES AND THOSE DEVICES INCORPORATING EMBEDDED DRAM
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|
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Patent #:
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|
Issue Dt:
|
07/27/2010
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Application #:
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12049244
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Filing Dt:
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03/14/2008
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Publication #:
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Pub Dt:
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09/17/2009
| | | | |
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Title:
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MULTI-BANK BLOCK ARCHITECTURE FOR INTEGRATED CIRCUIT MEMORY DEVICES HAVING NON-SHARED SENSE AMPLIFIER BANDS BETWEEN BANKS
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Patent #:
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|
Issue Dt:
|
11/09/2010
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Application #:
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12049248
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Filing Dt:
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03/14/2008
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Publication #:
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Pub Dt:
|
09/17/2009
| | | | |
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Title:
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ASYMETRIC DATA PATH POSITION AND DELAYS TECHNIQUE ENABLING HIGH SPEED ACCESS IN INTEGRATED CIRCUIT MEMORY DEVICES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/01/2009
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Application #:
|
12053401
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Filing Dt:
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03/21/2008
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|
Publication #:
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|
Pub Dt:
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09/24/2009
| | | | |
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Title:
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LOW SKEW DIFFERENTIAL AMPLIFIER USING TAIL VOLTAGE REFERENCE AND TAIL FEEDBACK
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|
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Patent #:
|
|
Issue Dt:
|
08/10/2010
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Application #:
|
12128456
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Filing Dt:
|
05/28/2008
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|
Publication #:
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Pub Dt:
|
12/03/2009
| | | | |
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Title:
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PHOTOLITHOGRAPHY WITH OPTICAL MASKS HAVING MORE TRANSPARENT FEATURES SURROUNDED BY LESS TRANSPARENT FEATURES
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|
|
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Patent #:
|
|
Issue Dt:
|
12/14/2010
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Application #:
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12128996
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Filing Dt:
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05/29/2008
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|
Publication #:
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Pub Dt:
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12/03/2009
| | | | |
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Title:
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METHOD OF REPAIRING DEEP SUBSURFACE DEFECTS IN A SILICON SUBSTRATE THAT INCLUDES DIFFUSING NEGATIVELY CHARGED IONS INTO THE SUBSTRATE FROM A SACRIFICIAL OXIDE LAYER
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|
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Patent #:
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|
Issue Dt:
|
11/26/2013
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Application #:
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12129556
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Filing Dt:
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05/29/2008
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Publication #:
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Pub Dt:
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12/03/2009
| | | | |
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Title:
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SHIELDING OF DATALINES WITH PHYSICAL PLACEMENT BASED ON TIME STAGGERED ACCESS
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|
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Patent #:
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Issue Dt:
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06/15/2010
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Application #:
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12134834
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Filing Dt:
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06/06/2008
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|
Publication #:
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Pub Dt:
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12/10/2009
| | | | |
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Title:
|
NONVOLATILE MEMORIES WITH TUNNEL DIELECTRIC WITH CHLORINE
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|
|
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Patent #:
|
|
Issue Dt:
|
10/05/2010
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Application #:
|
12145681
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Filing Dt:
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06/25/2008
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|
Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
|
Title:
|
INTEGRATED CIRCUITS WITH SUBSTRATE PROTRUSIONS, INCLUDING (BUT NOT LIMITED TO) FLOATING GATE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
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Application #:
|
12196067
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Filing Dt:
|
08/21/2008
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|
Publication #:
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Pub Dt:
|
02/25/2010
| | | | |
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Title:
|
FABRICATION OF INTEGRATED CIRCUITS WITH ISOLATION TRENCHES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/24/2010
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Application #:
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12207179
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Filing Dt:
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09/09/2008
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Publication #:
|
|
Pub Dt:
|
03/11/2010
| | | | |
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Title:
|
HIGH CAPACITIVE LOAD AND NOISE TOLERANT SYSTEM AND METHOD FOR CONTROLLING THE DRIVE STRENGTH OF OUTPUT DRIVERS IN INTEGRATED CIRCUIT DEVICES
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|
|
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Patent #:
|
|
Issue Dt:
|
01/25/2011
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Application #:
|
12275179
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Filing Dt:
|
11/20/2008
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|
Publication #:
|
|
Pub Dt:
|
05/20/2010
| | | | |
|
Title:
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CONFIGURABLE ARCHITECTURE HYBRID ANALOG/DIGITAL DELAY LOCKED LOOP (DLL) AND TECHNIQUE WITH FAST OPEN LOOP DIGITAL LOCKING FOR INTEGRATED CIRCUIT DEVICES
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|
|
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|
Patent #:
|
|
Issue Dt:
|
12/25/2012
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Application #:
|
12834696
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Filing Dt:
|
07/12/2010
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|
Publication #:
|
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Pub Dt:
|
01/12/2012
| | | | |
|
Title:
|
DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAM
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12834721
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Filing Dt:
|
07/12/2010
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
|
Title:
|
DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
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Application #:
|
12940507
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Filing Dt:
|
11/05/2010
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICES WITH GATE ELECTRODES AND WITH MONOCRYSTALLINE SILICON REGIONS THAT CONTAIN ATOMS OF NITROGEN AND ONE OR MORE OF CHLORINE, BROMINE, SULFUR, FLUORINE, OR PHOSPHORUS
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