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Patent Assignment Details
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Reel/Frame:008816/0783   Pages: 11
Recorded: 11/10/1997
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 8
1
Patent #:
Issue Dt:
07/28/1998
Application #:
08603222
Filing Dt:
02/20/1996
Title:
METHODS FOR ALLOCATING CIRCUIT DESIGN PORTIONS AMONG PHYSICAL CIRCUIT PORTIONS
2
Patent #:
Issue Dt:
08/18/1998
Application #:
08607849
Filing Dt:
02/27/1996
Title:
TRI-STATABLE INPUT/OUTPUT CIRCUITRY FOR PROGRAMMABLE LOGIC
3
Patent #:
Issue Dt:
06/16/1998
Application #:
08617664
Filing Dt:
03/13/1996
Title:
METHOD AND APPARATUS FOR SECURING PROGRAMMING DATA OF A PROGRAMMABLE LOGIC DEVICE
4
Patent #:
Issue Dt:
12/02/1997
Application #:
08619072
Filing Dt:
03/20/1996
Title:
PROGRAMMABLE LOGIC ARRAY INTEGRATED CIRCUITS WITH IMPROVED INTERCONNECTION CONDUCTOR UTILIZATION
5
Patent #:
Issue Dt:
02/23/1999
Application #:
08619073
Filing Dt:
03/20/1996
Title:
METHODS FOR IMPLEMENTING CIRCUIT DESIGNS IN PHYSICAL CIRCUITS
6
Patent #:
Issue Dt:
08/17/1999
Application #:
08631667
Filing Dt:
04/09/1996
Title:
INTEGRATED CIRCUIT PAD STRUCTURES
7
Patent #:
Issue Dt:
12/16/1997
Application #:
08634508
Filing Dt:
04/18/1996
Title:
PROGRAMMABLE VOLTAGE SUPPLY CIRCUITRY
8
Patent #:
Issue Dt:
12/02/1997
Application #:
08656448
Filing Dt:
05/31/1996
Title:
METHOD OF FABRICATING INTEGRATED CIRCUITS
Assignor
1
Exec Dt:
06/18/1997
Assignee
1
101 INNOVATION DRIVE
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
FISH & NEAVE
ROBERT R. JACKS0N
50TH FLOOR
1251 AVENUE OF THE AMERICAS
NEW YORK, NY 10020

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