Patent Assignment Details
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| Reel/Frame: | 021204/0789 | |
| Pages: | 2 |
| | Recorded: | 06/30/2008 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11173896
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Filing Dt:
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06/30/2005
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Publication #:
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Pub Dt:
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01/12/2006
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Title:
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Method and system for correcting low latency errors in read and write non volatile memories, particularly of the flash type
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Assignee
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| VIA C. OLIVETTI, 2 |
| AGRATE BRIANZA (MI), ITALY I-20041 |
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Correspondence name and address
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JAMES J. CARTER
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GRAYBEAL JACKSON HALEY LLP
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155 - 108TH AVENUE NE
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SUITE 350
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BELLEVUE, WA 98004-5973
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