Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 046594/0791 | |
| Pages: | 3 |
| | Recorded: | 08/09/2018 | | |
Attorney Dkt #: | 075803.000002 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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11/03/2009
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Application #:
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11051997
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Filing Dt:
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02/04/2005
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Publication #:
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Pub Dt:
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08/10/2006
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Title:
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INTERFACING EXTERNAL THREAD PRIORITIZING POLICY ENFORCING LOGIC WITH CUSTOMER MODIFIABLE REGISTER TO PROCESSOR INTERNAL SCHEDULER
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Patent #:
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Issue Dt:
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08/10/2010
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Application #:
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11681610
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Filing Dt:
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03/02/2007
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Publication #:
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Pub Dt:
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04/17/2008
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Title:
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HORIZONTALLY-SHARED CACHE VICTIMS IN MULTIPLE CORE PROCESSORS
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Patent #:
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Issue Dt:
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04/04/2017
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Application #:
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15019132
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Filing Dt:
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02/09/2016
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Publication #:
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Pub Dt:
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06/02/2016
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Title:
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Migration of Data to Register File Cache
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Patent #:
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Issue Dt:
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01/22/2019
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Application #:
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15824613
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Filing Dt:
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11/28/2017
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Publication #:
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Pub Dt:
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03/29/2018
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Title:
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Translation Lookaside Buffer
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Patent #:
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Issue Dt:
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06/09/2020
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Application #:
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15833555
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Filing Dt:
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12/06/2017
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Publication #:
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Pub Dt:
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04/05/2018
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Title:
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Migration of Data to Register File Cache
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Patent #:
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Issue Dt:
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08/13/2019
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Application #:
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15874724
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Filing Dt:
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01/18/2018
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Publication #:
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Pub Dt:
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05/24/2018
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Title:
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Decoding Instructions That Are Modified By One Or More Other Instructions
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Assignee
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IMAGINATION HOUSE |
HOME PARK ESTATE |
KINGS LANGLEY, UNITED KINGDOM WD4 8LZ |
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Correspondence name and address
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VORYS, SATER, SEYMOUR AND PEASE LLP
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1909 K STREET, N.W.
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9TH FLOOR
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WASHINGTON, DC 20006
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