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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:021336/0797   Pages: 20
Recorded: 07/31/2008
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 7
1
Patent #:
Issue Dt:
05/04/2010
Application #:
11952495
Filing Dt:
12/07/2007
Publication #:
Pub Dt:
03/26/2009
Title:
LARGE SUBSTRATE STRUCTURAL VIAS
2
Patent #:
Issue Dt:
11/09/2010
Application #:
11975007
Filing Dt:
10/16/2007
Publication #:
Pub Dt:
03/26/2009
Title:
SEMICONDUCTOR SUBSTRATE ELASTOMERIC STACK
3
Patent #:
Issue Dt:
07/27/2010
Application #:
11975011
Filing Dt:
10/16/2007
Publication #:
Pub Dt:
03/26/2009
Title:
COMB-SHAPED POWER BUS BAR ASSEMBLY STRUCTURE HAVING INTEGRATED CAPACITORS
4
Patent #:
Issue Dt:
08/16/2011
Application #:
11975058
Filing Dt:
10/16/2007
Publication #:
Pub Dt:
03/26/2009
Title:
PREVENTING BREAKAGE OF LONG METAL SIGNAL CONDUCTORS ON SEMICONDUCTOR SUBSTRATES
5
Patent #:
Issue Dt:
05/17/2011
Application #:
11975966
Filing Dt:
10/22/2007
Publication #:
Pub Dt:
03/26/2009
Title:
INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE USING INCOMPATIBLE PROCESSES
6
Patent #:
Issue Dt:
11/09/2010
Application #:
11981853
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
03/26/2009
Title:
LOCAL DEFECT MEMORIES ON SEMICONDUCTOR SUBSTRATES IN A STACK COMPUTER
7
Patent #:
Issue Dt:
05/18/2010
Application #:
11999747
Filing Dt:
12/07/2007
Publication #:
Pub Dt:
03/26/2009
Title:
STACKABLE SELF-ALIGNING INSULATIVE GUIDE TRAY FOR HOLDING SEMICONDUCTOR SUBSTRATES
Assignor
1
Exec Dt:
06/04/2008
Assignee
1
P.O. BOX 14245
RESEARCH TRIANGLE PARK, NORTH CAROLINA 27709
Correspondence name and address
IMPERIUM PATENT WORKS
ZHENG JIN
P.O. BOX 587
SUNOL, CA 94586

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