Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 021336/0797 | |
| Pages: | 20 |
| | Recorded: | 07/31/2008 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
7
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Patent #:
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Issue Dt:
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05/04/2010
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Application #:
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11952495
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Filing Dt:
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12/07/2007
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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LARGE SUBSTRATE STRUCTURAL VIAS
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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11975007
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Filing Dt:
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10/16/2007
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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SEMICONDUCTOR SUBSTRATE ELASTOMERIC STACK
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Patent #:
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Issue Dt:
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07/27/2010
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Application #:
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11975011
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Filing Dt:
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10/16/2007
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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COMB-SHAPED POWER BUS BAR ASSEMBLY STRUCTURE HAVING INTEGRATED CAPACITORS
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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11975058
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Filing Dt:
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10/16/2007
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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PREVENTING BREAKAGE OF LONG METAL SIGNAL CONDUCTORS ON SEMICONDUCTOR SUBSTRATES
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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11975966
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Filing Dt:
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10/22/2007
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE USING INCOMPATIBLE PROCESSES
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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11981853
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Filing Dt:
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10/31/2007
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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LOCAL DEFECT MEMORIES ON SEMICONDUCTOR SUBSTRATES IN A STACK COMPUTER
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Patent #:
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Issue Dt:
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05/18/2010
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Application #:
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11999747
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Filing Dt:
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12/07/2007
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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STACKABLE SELF-ALIGNING INSULATIVE GUIDE TRAY FOR HOLDING SEMICONDUCTOR SUBSTRATES
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Assignee
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P.O. BOX 14245 |
RESEARCH TRIANGLE PARK, NORTH CAROLINA 27709 |
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Correspondence name and address
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IMPERIUM PATENT WORKS
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ZHENG JIN
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P.O. BOX 587
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SUNOL, CA 94586
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