Total properties:
22
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
09187197
|
Filing Dt:
|
11/03/1998
|
Title:
|
SHALLOW TRENCH ISOLATION METHOD FOR A SEMICONDUCTOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
09216078
|
Filing Dt:
|
12/18/1998
|
Title:
|
METHOD OF SIMULTANEOUSLY IMPLEMENTING DIFFERENTIAL GATE OXIDE THICKNESS USING FLUORINE BEARING IMPURITIES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
09796166
|
Filing Dt:
|
02/28/2001
|
Publication #:
|
|
Pub Dt:
|
01/24/2002
| | | | |
Title:
|
APPARATUS AND METHOD FOR CONTROLLING BOILING CONDITIONS OF HOT PHOSPHORIC ACID SOLUTION WITH PRESSURE ADJUSTMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
10029930
|
Filing Dt:
|
12/31/2001
|
Publication #:
|
|
Pub Dt:
|
07/04/2002
| | | | |
Title:
|
HEATING LAMP BRACKETS FOR REACTION CHAMBERS OF EVAPORATION COATING MACHINES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10074859
|
Filing Dt:
|
02/11/2002
|
Publication #:
|
|
Pub Dt:
|
09/05/2002
| | | | |
Title:
|
RUBBER PLATE USED IN AN ION IMPLANTER AND METHOD OF PREPARING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
10113705
|
Filing Dt:
|
03/27/2002
|
Publication #:
|
|
Pub Dt:
|
10/03/2002
| | | | |
Title:
|
METALLIZATION PROCESS TO REDUCE STRESS BETWEEN ALCU LAYER AND TITANIUM NITRIDE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2004
|
Application #:
|
10133087
|
Filing Dt:
|
04/25/2002
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
Title:
|
METHOD OF REDUCING BORON OUTGASSING AT TRENCH POWER IC'S OXIDATION PROCESS FOR SACRIFICIAL OXIDE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10218376
|
Filing Dt:
|
08/12/2002
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
Title:
|
DETERMINING EXPOSURE TIME OF WAFER PHOTOLITHOGRAPHY PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2004
|
Application #:
|
10219092
|
Filing Dt:
|
08/13/2002
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
Title:
|
TRANSISTOR WITH HIGHLY UNIFORM THRESHOLD VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10219094
|
Filing Dt:
|
08/13/2002
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
Title:
|
PREVENTING GATE OXICE THINNING EFFECT IN A RECESS LOCOS PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10232260
|
Filing Dt:
|
08/29/2002
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
Title:
|
METHOD FOR FORMING DUAL OXIDE LAYERS AT BOTTOM OF TRENCH
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2004
|
Application #:
|
10263397
|
Filing Dt:
|
10/01/2002
|
Publication #:
|
|
Pub Dt:
|
04/10/2003
| | | | |
Title:
|
METHOD OF MAKING IC CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10346513
|
Filing Dt:
|
01/15/2003
|
Publication #:
|
|
Pub Dt:
|
10/02/2003
| | | | |
Title:
|
METHOD FOR DETERMINING CHEMICAL MECHANICAL POLISHING TIME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10397478
|
Filing Dt:
|
03/25/2003
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
Title:
|
NONVOLATILE MEMORIES WITH ASYMMETRIC TRANSISTORS, NONVOLATILE MEMORIES WITH HIGH VOLTAGE LINES EXTENDING IN THE COLUMN DIRECTION, AND NONVOLATILE MEMORIES WITH DECODING CIRCUITS SHARING A COMMON AREA
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
10453771
|
Filing Dt:
|
06/02/2003
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
Title:
|
METHOD OF FORMING A BOTTOM OXIDE LAYER IN A TRENCH
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10652442
|
Filing Dt:
|
08/28/2003
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
Title:
|
TERMINATION STRUCTURE FOR TRENCH DMOS DEVICE AND METHOD OF MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10652635
|
Filing Dt:
|
08/28/2003
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
Title:
|
TRENCH FILLING PROCESS FOR PREVENTING FORMATION OF VOIDS IN TRENCH
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10652664
|
Filing Dt:
|
08/28/2003
|
Publication #:
|
|
Pub Dt:
|
06/03/2004
| | | | |
Title:
|
LEAKAGE DETECTING METHOD FOR USE IN OXIDIZING SYSTEM OF FORMING OXIDE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10668434
|
Filing Dt:
|
09/22/2003
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
Title:
|
POWER METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10671814
|
Filing Dt:
|
09/26/2003
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
Title:
|
METHOD FOR ASSEMBLING A SCRUBBER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10677568
|
Filing Dt:
|
10/01/2003
|
Publication #:
|
|
Pub Dt:
|
10/14/2004
| | | | |
Title:
|
BOTTOM OXIDE FORMATION PROCESS FOR PREVENTING FORMATION OF VOIDS IN TRENCH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10976620
|
Filing Dt:
|
10/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
Rubber plate used in an ion implanter and method of preparing the same
|
|