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Total properties:
26
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Patent #:
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Issue Dt:
|
08/22/1989
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Application #:
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07236076
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Filing Dt:
|
08/24/1988
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Title:
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OPTOCOUPLER FOR POWER FET
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Patent #:
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Issue Dt:
|
09/10/1991
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Application #:
|
07406826
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Filing Dt:
|
09/12/1989
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Title:
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A SEMICONDUCTOR DIODE AND METHOD FOR MAKING IT
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Patent #:
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|
Issue Dt:
|
05/11/1993
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Application #:
|
07759190
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Filing Dt:
|
09/10/1991
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Title:
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PROCESS FOR EXTRACTING LOGIC FROM TRANSISTOR AND RESISTOR DATA REPRESENTATIONS OF CIRCUITS
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Patent #:
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Issue Dt:
|
05/10/1994
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Application #:
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07876640
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Filing Dt:
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04/30/1992
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Title:
|
PRINTED CIRCUIT BOARD FOR MOUNTED SEMICONDUCTORS AND OTHER ELECTRONIC COMPONENTS
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Patent #:
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Issue Dt:
|
10/25/1994
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Application #:
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08101637
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Filing Dt:
|
08/04/1993
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Title:
|
METHOD OF MANUFACTURING A PRINTED CIRCUIT BOARD
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Patent #:
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Issue Dt:
|
08/29/1995
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Application #:
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08110608
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Filing Dt:
|
08/23/1993
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Title:
|
SILICON CONTROLLED RECTIFIER WITH A VARIABLE BASE-SHUNT RESISTANCE
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Patent #:
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Issue Dt:
|
09/06/1994
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Application #:
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08128424
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Filing Dt:
|
09/29/1993
|
|
Title:
|
METHOD OF MAKING PEDESTAL LEAD FRAME FOR SUPPORTING A SEMICONDUCTOR CHIP
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/09/1996
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Application #:
|
08299717
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Filing Dt:
|
09/01/1994
|
|
Title:
|
METHOD OF MAKING SILICON CONTROLLED RECTIFIER WITH A VARIABLE BASE- SHUNT RESISTANCE
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|
|
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Patent #:
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|
Issue Dt:
|
04/09/1996
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Application #:
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08355452
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Filing Dt:
|
12/13/1994
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Title:
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SEMICONDUCTOR DEVICE AND LEAD FRAME COMBINATION
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|
|
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Patent #:
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|
Issue Dt:
|
03/03/1998
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Application #:
|
08537062
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Filing Dt:
|
09/29/1995
|
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
01/05/1999
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Application #:
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08579535
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Filing Dt:
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12/27/1995
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Title:
|
CLOSED-MOLD FOR LED ALPHANUMERIC DISPLAYS
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|
|
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Patent #:
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|
Issue Dt:
|
10/12/1999
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Application #:
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08623905
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Filing Dt:
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03/27/1996
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Title:
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BIPOLAR SILICON TRANSISTOR WITH ARSENIC AND PHOSPHOROUS RATIO
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|
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Patent #:
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Issue Dt:
|
07/07/1998
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Application #:
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08675590
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Filing Dt:
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07/03/1996
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Title:
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CIRCUIT ARRANGEMENT AND METHOD FOR MEASURING A DIFFERENCE IN CAPACITANCE BETWEEN A FIRST CAPACITANCE C1 AND A SECOND CAPACITANCE C2
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|
|
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Patent #:
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|
Issue Dt:
|
08/08/2000
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Application #:
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08940703
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Filing Dt:
|
09/30/1997
|
|
Title:
|
ALPHANUMERIC DISPLAY WITH 21-DOT MATRIX FORMAT
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|
|
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Patent #:
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|
Issue Dt:
|
10/24/2000
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Application #:
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09182495
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Filing Dt:
|
10/30/1998
|
|
Title:
|
COLUMN REDUNDANCY CIRCUIT WITH REDUCED SIGNAL PATH DELAY
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|
|
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Patent #:
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|
Issue Dt:
|
11/07/2000
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Application #:
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09193239
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Filing Dt:
|
11/17/1998
|
|
Title:
|
IMPROVED REDUNDANCY SELECTION CIRCUIT FOR SEMICONDUCTOR MEMORIES
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|
|
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Patent #:
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|
Issue Dt:
|
06/04/2002
|
Application #:
|
09642332
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Filing Dt:
|
08/21/2000
|
|
Title:
|
SYNCHRONOUS FEEDBACK DIGITAL CIRCUIT HAVING A MINIMZED SWITCHING POWER LOSS
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|
|
|
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Patent #:
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|
Issue Dt:
|
02/25/2003
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Application #:
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10036246
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Filing Dt:
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10/22/2001
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Publication #:
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Pub Dt:
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10/17/2002
| | | | |
|
Title:
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METHOD AND APPARATUS FOR DETERMINING INTERPOLATED INTERMEDIATE VALUES OF A SAMPLED SIGNAL
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|
|
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Patent #:
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|
Issue Dt:
|
08/31/2004
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Application #:
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10336851
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Filing Dt:
|
01/06/2003
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Publication #:
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Pub Dt:
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07/31/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ACCELERATING SIGNAL EQUALIZATION BETWEEN A PAIR OF SIGNAL LINES
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|
|
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Patent #:
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|
Issue Dt:
|
03/02/2004
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Application #:
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10420018
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Filing Dt:
|
04/18/2003
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Publication #:
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Pub Dt:
|
11/06/2003
| | | | |
|
Title:
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METHOD AND APPARATUS FOR ADAPTIVE DATA COMPRESSION
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/31/2009
|
Application #:
|
11747428
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Filing Dt:
|
05/11/2007
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Publication #:
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Pub Dt:
|
09/06/2007
| | | | |
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Title:
|
LOW POWER MATCH-LINE SENSING CIRCUIT
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/10/2009
|
Application #:
|
11787667
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Filing Dt:
|
04/17/2007
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|
Publication #:
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Pub Dt:
|
01/31/2008
| | | | |
|
Title:
|
CONTENT ADDRESSABLE MEMORY ARCHITECTURE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/15/2014
|
Application #:
|
12168091
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Filing Dt:
|
07/04/2008
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|
Publication #:
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Pub Dt:
|
06/18/2009
| | | | |
|
Title:
|
CLOCK REPRODUCING AND TIMING METHOD IN A SYSTEM HAVING A PLURALITY OF DEVICES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/07/2010
|
Application #:
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12236874
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Filing Dt:
|
09/24/2008
|
|
Publication #:
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|
Pub Dt:
|
01/22/2009
| | | | |
|
Title:
|
METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
12241832
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Filing Dt:
|
09/30/2008
|
|
Publication #:
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Pub Dt:
|
04/01/2010
| | | | |
|
Title:
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SERIAL-CONNECTED MEMORY SYSTEM WITH OUTPUT DELAY ADJUSTMENT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
12241960
|
Filing Dt:
|
09/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
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Title:
|
SERIAL-CONNECTED MEMORY SYSTEM WITH DUTY CYCLE CORRECTION
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|
