Patent Assignment Details
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| Reel/Frame: | 016700/0816 | |
| Pages: | 2 |
| | Recorded: | 06/23/2005 | | |
| Conveyance: | RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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01/18/1994
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Application #:
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07461492
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Filing Dt:
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01/05/1990
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Title:
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SCALABLE PROCESSOR TO PROCESSOR AND PROCESSOR- TO -I/O INTERCONNECTION NETWORK AND METHOD FOR PARALLEL PROCESSING ARRAYS
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Patent #:
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Issue Dt:
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05/17/1994
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Application #:
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07461572
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Filing Dt:
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01/05/1990
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Title:
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SYSTEM HAVING FIXEDLY PRIORIZED AND GROUPED BY POSITIONS I/O LINES FOR INTERCONNECTING ROUTER ELEMENTS IN PLURALITY OF STAGES WITHIN PARRA- LLEL COMPUTER
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Patent #:
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Issue Dt:
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09/06/1994
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Application #:
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07693846
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Filing Dt:
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04/30/1991
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Title:
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ROUTER CHIP WITH QUAD-CROSSBAR AND HYPERBAR PERSONALITIES
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Patent #:
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Issue Dt:
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09/07/1993
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Application #:
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07802944
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Filing Dt:
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12/06/1991
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Title:
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INPUT/OUTPUT SYSTEM FOR PARALLEL PROCESSING ARRAYS
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Assignee
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| 760 MARY AVE. |
| SUNNYVALE, CALIFORNIA 94086 |
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Correspondence name and address
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SILICON VALLEY BANK
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LOAN DOCUMENTATION HA155
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3003 TASMAN DR.
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SANTA CLARA, CA 95054
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