Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 037282/0817 | |
| Pages: | 151 |
| | Recorded: | 12/14/2015 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14340054
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Filing Dt:
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07/24/2014
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Publication #:
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Pub Dt:
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11/13/2014
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Title:
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HIGH VOLTAGE GATE FORMATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14566462
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Filing Dt:
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12/10/2014
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Publication #:
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Pub Dt:
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04/02/2015
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Title:
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Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device
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Assignee
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| 198 CHAMPION COURT |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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CYPRESS SEMICONDUCTOR CORPORATION
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198 CHAMPION COURT
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SAN JOSE, CA 95134
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