|
Total properties:
32
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/1995
|
Application #:
|
08037893
|
Filing Dt:
|
03/26/1993
|
|
Title:
|
FLASH MEMORY MASS STORAGE ARCHITECTURE INCORPORATING WEAR LEVELING TECHNIQUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/1995
|
Application #:
|
08038668
|
Filing Dt:
|
03/26/1993
|
|
Title:
|
FLASH MEMORY MASS STORAGE ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/1996
|
Application #:
|
08131495
|
Filing Dt:
|
10/04/1993
|
|
Title:
|
FLASH MEMORY MASS STORAGE ARCHITECTURE INCORPORATING WEAR LEVELING TECHNIQUE WITHOUT USING CAM CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/1997
|
Application #:
|
08326884
|
Filing Dt:
|
10/21/1994
|
|
Title:
|
METHOD AND APPARATUS FOR COMBINING CONTROLLER FIRMWARE STORAGE AND CONTROLLER LOGIC IN A MASS STORAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1998
|
Application #:
|
08420239
|
Filing Dt:
|
04/11/1995
|
|
Title:
|
HIGH PERFORMANCE METHOD OF AND SYSTEM FOR SELECTING ONE OF A PLURALITY OF IC CHIPS WHILE REQUIRING MINIMAL SELECT LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/1998
|
Application #:
|
08509706
|
Filing Dt:
|
07/31/1995
|
|
Title:
|
DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/1997
|
Application #:
|
08515188
|
Filing Dt:
|
08/15/1995
|
|
Title:
|
A NON-VOLATILE MEMORY SYSTEM OF MULTI-LEVEL TRANSISTOR CELLS AND METHODS USING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08527484
|
Filing Dt:
|
09/13/1995
|
|
Title:
|
METHOD OF AND ARCHITECTURE FOR CONTROLLING SYSTEM DATA WITH AUTOMATIC WEAR LEVELING IN A SEMICONDUCTOR NON-VOLATILE MASS STORAGE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1998
|
Application #:
|
08748867
|
Filing Dt:
|
11/13/1996
|
|
Title:
|
AUTOMATIC VOLTAGE DETECTION IN MULTIPLE VOLTAGE APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08795072
|
Filing Dt:
|
02/05/1997
|
|
Title:
|
METHOD AND APPARATUS FOR VERIFYING ERASURE OF MEMORY BLOCKS WITHIN A NON-VOLATILE MEMORY STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/1999
|
Application #:
|
08831266
|
Filing Dt:
|
03/31/1997
|
|
Title:
|
MOVING SECTORS WITHIN A BLOCK OF INFORMATION IN A FLASH MEMORY MASS STORAGE ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/1998
|
Application #:
|
08858847
|
Filing Dt:
|
05/19/1997
|
|
Title:
|
IDENTIFICATION AND VERIFICATION OF A SECTOR WITHIN A BLOCK OF MASS STORAGE FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08946331
|
Filing Dt:
|
10/07/1997
|
|
Title:
|
MOVING SEQUENTIAL SECTORS WITHIN A BLOCK OF INFORMATION IN A FLASH MEMORY MASS STORAGE ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
08976557
|
Filing Dt:
|
11/24/1997
|
|
Title:
|
ALIGNMENT OF CLUSTER ADDRESS TO BLOCK ADDRESSES WITHIN A SEMICONDUCTOR NON-VOLATILE MASS STORAGE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08988844
|
Filing Dt:
|
12/11/1997
|
|
Title:
|
METHOD AND APPARATUS FOR STORING LOCATION IDENTIFICATION INFORMATION WITHIN NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09030697
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
INCREASING THE MEMORY PERFORMANCE OF FLASH MEMORY DEVICES BY WRITING SECTORS SIMULTANEOUSLY TO MULTIPLE FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09034173
|
Filing Dt:
|
03/02/1998
|
|
Title:
|
AN EXTERNALLY COUPLED COMPACT FLASH MEMORY CARD THAT CONFIGURES ITSELF ONE OF A PLURALITY OF APPROPRIATE OPERATING PROTOCOL MODES OF A HOST COMPUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
09047798
|
Filing Dt:
|
03/25/1998
|
|
Title:
|
FLASH MEMORY LEVELING ARCHITECTURE HAVING NO EXTERNAL LATCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2000
|
Application #:
|
09052038
|
Filing Dt:
|
03/30/1998
|
|
Title:
|
INTERNAL CMOS REFERENCE GENERATOR AND VOLTAGE REGULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
09087720
|
Filing Dt:
|
05/29/1998
|
|
Title:
|
DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
09111414
|
Filing Dt:
|
07/07/1998
|
|
Title:
|
METHOD AND APPARATUS FOR PERFORMING ERASE OPERATIONS TRANSPARENT TO A SOLID STATE STORAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09156951
|
Filing Dt:
|
09/18/1998
|
|
Title:
|
IDENTIFICATION AND VERIFICATION OF A SECTOR WITHIN A BLOCK OF MASS STORAGE FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09234430
|
Filing Dt:
|
01/20/1999
|
|
Title:
|
SYSTEM FOR CONFIGURING A FLASH MEMORY CARD TO A SELECTED OPERATING MODE BY MONITORING AN UNENCODED SIGNAL FROM A HOST AND AN ENCODED SIGNAL IN THE CARD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
09258163
|
Filing Dt:
|
02/25/1999
|
|
Title:
|
METHOD OF INCREASING DATA RELIABILITY OF A FLASH MEMORY DEVICE WITHOUT COMPROMISING COMPATIBILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09264340
|
Filing Dt:
|
03/08/1999
|
|
Title:
|
MOVING SECTORS WITHIN A BLOCK OF INFORMATION IN A FLASH MEMORY MASS STORAGE ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09265192
|
Filing Dt:
|
03/10/1999
|
|
Title:
|
INTERNAL OSCILLATOR CIRCUIT INCLUDING A RING OSCILLATOR CONTROLLED BY A VOLTAGE REGULATOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
09283728
|
Filing Dt:
|
04/01/1999
|
|
Title:
|
SPACE MANAGEMENT FOR MANAGING HIGH CAPACITY NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09311045
|
Filing Dt:
|
05/13/1999
|
|
Title:
|
DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09330278
|
Filing Dt:
|
06/11/1999
|
|
Title:
|
METHOD AND APPARATUS FOR DECREASING BLOCK WRITE OPERATION TIMES PERFORMED ON NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09440986
|
Filing Dt:
|
11/16/1999
|
|
Title:
|
DATA PIPELINING METHOD AND APPARATUS FOR MEMORY CONTROL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09487865
|
Filing Dt:
|
01/20/2000
|
|
Title:
|
Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09565517
|
Filing Dt:
|
05/05/2000
|
|
Title:
|
Nonvolatile memory using flexible erasing methods and method and system for using same
|
|
