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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:017197/0826   Pages: 5
Recorded: 02/22/2006
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14
1
Patent #:
Issue Dt:
04/15/2008
Application #:
11313650
Filing Dt:
12/22/2005
Publication #:
Pub Dt:
06/28/2007
Title:
GATE INDUCED DRAIN LEAKAGE CURRENT REDUCTION BY VOLTAGE REGULATION OF MASTER WORDLINE
2
Patent #:
Issue Dt:
11/06/2007
Application #:
11324700
Filing Dt:
01/03/2006
Publication #:
Pub Dt:
07/05/2007
Title:
INTEGRATED CIRCUIT HAVING A RESISTIVE MEMORY
3
Patent #:
NONE
Issue Dt:
Application #:
11331454
Filing Dt:
01/13/2006
Publication #:
Pub Dt:
07/19/2007
Title:
Patterning methods and masks
4
Patent #:
Issue Dt:
04/22/2008
Application #:
11333037
Filing Dt:
01/17/2006
Publication #:
Pub Dt:
07/19/2007
Title:
TEST PARALLELISM INCREASE BY TESTER CONTROLLABLE SWITCHING OF CHIP SELECT GROUPS
5
Patent #:
NONE
Issue Dt:
Application #:
11333043
Filing Dt:
01/17/2006
Publication #:
Pub Dt:
07/19/2007
Title:
Local wordline driver scheme to avoid fails due to floating wordline in a segmented wordline driver scheme
6
Patent #:
Issue Dt:
12/01/2009
Application #:
11334704
Filing Dt:
01/18/2006
Publication #:
Pub Dt:
07/19/2007
Title:
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
7
Patent #:
NONE
Issue Dt:
Application #:
11334850
Filing Dt:
01/19/2006
Publication #:
Pub Dt:
07/19/2007
Title:
Defect reduction in immersion lithography
8
Patent #:
Issue Dt:
02/10/2009
Application #:
11337754
Filing Dt:
01/23/2006
Publication #:
Pub Dt:
07/26/2007
Title:
SYSTEM METHOD FOR PERFORMING A DIRECT MEMORY ACCESS FOR AUTOMATICALLY COPYING INITIALIZATION BOOT CODE IN A NEW MEMORY ARCHITECTURE
9
Patent #:
NONE
Issue Dt:
Application #:
11338042
Filing Dt:
01/24/2006
Publication #:
Pub Dt:
07/26/2007
Title:
PHASE DETECTOR
10
Patent #:
Issue Dt:
07/05/2011
Application #:
11338059
Filing Dt:
01/24/2006
Publication #:
Pub Dt:
07/26/2007
Title:
POROUS SILICON DIELECTRIC
11
Patent #:
NONE
Issue Dt:
Application #:
11339745
Filing Dt:
01/25/2006
Publication #:
Pub Dt:
07/26/2007
Title:
DOUBLE-DATA-RATE (DDR) SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) CAPABLE OF GENERATING A MINIMUM RAS-TO-CAS DELAY (TRCD)
12
Patent #:
Issue Dt:
08/30/2011
Application #:
11343161
Filing Dt:
01/30/2006
Publication #:
Pub Dt:
08/02/2007
Title:
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
13
Patent #:
NONE
Issue Dt:
Application #:
11347867
Filing Dt:
02/06/2006
Publication #:
Pub Dt:
08/09/2007
Title:
Debris apparatus, system, and method
14
Patent #:
Issue Dt:
11/11/2008
Application #:
11349631
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
08/09/2007
Title:
SHARED INTERFACE FOR COMPONENTS IN AN EMBEDDED SYSTEM
Assignor
1
Exec Dt:
02/22/2006
Assignee
1
ST.-MARTIN-STR. 53
MUNICH, GERMANY 81669
Correspondence name and address
HEATHER ROWLAND
3000 CENTREGREEN WAY
CARY, NC 27513

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