Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 026868/0831 | |
| Pages: | 6 |
| | Recorded: | 09/07/2011 | | |
| Attorney Dkt #: | TIER-GEN |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
9
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Patent #:
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Issue Dt:
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11/04/2008
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Application #:
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11985822
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Filing Dt:
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11/19/2007
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Publication #:
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Pub Dt:
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03/27/2008
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Title:
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THREE DIMENSIONAL INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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12/16/2008
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Application #:
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11985830
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Filing Dt:
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11/19/2007
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Publication #:
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Pub Dt:
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03/20/2008
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Title:
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LOOK-UP TABLE STRUCTURE WITH EMBEDDED CARRY LOGIC
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Patent #:
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Issue Dt:
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03/16/2010
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Application #:
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12032667
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Filing Dt:
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02/16/2008
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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PROGRAMMABLE INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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12/09/2008
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Application #:
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12045635
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Filing Dt:
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03/10/2008
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Publication #:
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Pub Dt:
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06/26/2008
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Title:
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ALTERABLE APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC)
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Patent #:
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Issue Dt:
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07/30/2013
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Application #:
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12104377
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Filing Dt:
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04/16/2008
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Publication #:
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Pub Dt:
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09/11/2008
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Title:
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Timing Exact Design Conversions from FPGA to ASIC
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Patent #:
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Issue Dt:
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05/26/2009
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Application #:
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12105259
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Filing Dt:
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04/17/2008
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Publication #:
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Pub Dt:
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08/14/2008
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Title:
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THREE DIMENSIONAL INTEGRATED CIRCUITS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12207064
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Filing Dt:
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09/09/2008
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Publication #:
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Pub Dt:
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01/01/2009
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Title:
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THIN FILM TRANSISTORS AND FABRICATION METHODS
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Patent #:
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Issue Dt:
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05/04/2010
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Application #:
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12207110
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Filing Dt:
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09/09/2008
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Publication #:
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Pub Dt:
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01/01/2009
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Title:
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SEMICONDUCTOR SWITCHING DEVICES AND FABRICATION METHODS
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Patent #:
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Issue Dt:
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02/02/2010
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Application #:
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12254629
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Filing Dt:
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10/20/2008
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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THREE DIMENSIONAL INTEGRATED CIRCUITS
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Assignee
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| 882 LOUISE DRIVE |
| SUNNYVALE, CALIFORNIA 94087 |
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Correspondence name and address
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MURABITO, HAO & BARNES LLP
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TWO NORTH MARKET STREET
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THIRD FLOOR
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SAN JOSE, CA 95113
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