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Reel/Frame:043669/0832   Pages: 5
Recorded: 09/22/2017
Attorney Dkt #:S4137-0145
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 33
1
Patent #:
6604203
Issue Dt:
08/05/2003
Application #:
09394376
Filing Dt:
09/10/1999
Title:
APPARATUS AND METHOD FOR SELF-SYNCHRONIZATION OF DATA TO A LOCAL CLOCK
2
Patent #:
6625151
Issue Dt:
09/23/2003
Application #:
09420909
Filing Dt:
10/20/1999
Title:
MULTICASTING METHOD AND ARRANGEMENT
3
Patent #:
6754742
Issue Dt:
06/22/2004
Application #:
09428285
Filing Dt:
10/27/1999
Title:
QUEUE MANAGEMENT SYSTEM PERFORMING ONE READ ONE WRITE DURING ONE CYCLE BY USING FREE QUEUES
4
Patent #:
7016346
Issue Dt:
03/21/2006
Application #:
09469979
Filing Dt:
12/21/1999
Title:
APPARATUS AND METHOD FOR CONVERTING DATA IN SERIAL FORMAT TO PARALLEL FORMAT AND VICE VERSA
5
Patent #:
7215678
Issue Dt:
05/08/2007
Application #:
09546494
Filing Dt:
04/10/2000
Title:
METHOD AND APPARATUS FOR DISTRIBUTION OF BANDWIDTH IN A SWITCH
6
Patent #:
6977940
Issue Dt:
12/20/2005
Application #:
09560105
Filing Dt:
04/28/2000
Title:
METHOD AND ARRANGEMENT FOR MANAGING PACKET QUEUES IN SWITCHES
7
Patent #:
6330177
Issue Dt:
12/11/2001
Application #:
09574354
Filing Dt:
05/19/2000
Title:
CAM/RAM memory device with a scalable structure
8
Patent #:
7061868
Issue Dt:
06/13/2006
Application #:
09697708
Filing Dt:
10/25/2000
Title:
METHOD FOR FLOW CONTROL IN A SWITCH AND A SWITCH CONTROLLED THEREBY
9
Patent #:
7002983
Issue Dt:
02/21/2006
Application #:
09738720
Filing Dt:
12/15/2000
Publication #:
US20010046238
Pub Dt:
11/29/2001
Title:
DEVICE FOR DATASTREAM DECODING
10
Patent #:
6944171
Issue Dt:
09/13/2005
Application #:
09804591
Filing Dt:
03/12/2001
Publication #:
US20020126683
Pub Dt:
09/12/2002
Title:
SCHEDULER METHOD AND DEVICE IN A SWITCH
11
Patent #:
6477071
Issue Dt:
11/05/2002
Application #:
09850882
Filing Dt:
05/07/2001
Publication #:
US20020163823
Pub Dt:
11/07/2002
Title:
METHOD AND APPARATUS FOR CONTENT ADDRESSABLE MEMORY WITH A PARTITIONED MATCH LINE
12
Patent #:
7158529
Issue Dt:
01/02/2007
Application #:
11255759
Filing Dt:
10/21/2005
Publication #:
US20060034312
Pub Dt:
02/16/2006
Title:
DEVICE FOR DATASTREAM DECODING
13
Patent #:
8572539
Issue Dt:
10/29/2013
Application #:
12265585
Filing Dt:
11/05/2008
Publication #:
US20090115503
Pub Dt:
05/07/2009
Title:
VARIABILITY-AWARE SCHEME FOR HIGH-PERFORMANCE ASYNCHRONOUS CIRCUIT VOLTAGE REGLULATION
14
Patent #:
8433875
Issue Dt:
04/30/2013
Application #:
12711909
Filing Dt:
02/24/2010
Publication #:
US20110204932
Pub Dt:
08/25/2011
Title:
ASYNCHRONOUS SCHEME FOR CLOCK DOMAIN CROSSING
15
Patent #:
9263409
Issue Dt:
02/16/2016
Application #:
14283108
Filing Dt:
05/20/2014
Publication #:
US20140346513
Pub Dt:
11/27/2014
Title:
Mixed-Sized Pillars That Are Probeable and Routable
16
Patent #:
9461000
Issue Dt:
10/04/2016
Application #:
14283113
Filing Dt:
05/20/2014
Publication #:
US20140346678
Pub Dt:
11/27/2014
Title:
PARALLEL SIGNAL VIA STRUCTURE
17
Patent #:
9435846
Issue Dt:
09/06/2016
Application #:
14283116
Filing Dt:
05/20/2014
Publication #:
US20140347089
Pub Dt:
11/27/2014
Title:
TESTING OF THRU-SILICON VIAS
18
Patent #:
9762261
Issue Dt:
09/12/2017
Application #:
14502954
Filing Dt:
09/30/2014
Publication #:
US20150095738
Pub Dt:
04/02/2015
Title:
Error Detection and Correction in Ternary Content Addressable Memory (TCAM)
19
Patent #:
9529669
Issue Dt:
12/27/2016
Application #:
14502966
Filing Dt:
09/30/2014
Publication #:
US20150095740
Pub Dt:
04/02/2015
Title:
ERROR DETECTION AND CORRECTION IN BINARY CONTENT ADDRESSABLE MEMORY (BCAM)
20
Patent #:
9852250
Issue Dt:
12/26/2017
Application #:
14628105
Filing Dt:
02/20/2015
Publication #:
US20160246910
Pub Dt:
08/25/2016
Title:
Memory Optimization in VLSI Design Using Generic Memory Models
21
Patent #:
9727681
Issue Dt:
08/08/2017
Application #:
14628668
Filing Dt:
02/23/2015
Publication #:
US20160246909
Pub Dt:
08/25/2016
Title:
Generating Specific Memory Models Using Generic Memory Models for Designing Memories in VLSI Design
22
Patent #:
9727682
Issue Dt:
08/08/2017
Application #:
14628676
Filing Dt:
02/23/2015
Publication #:
US20160246911
Pub Dt:
08/25/2016
Title:
Designing Memories in VLSI Design Using Specific Memory Models Generated from Generic Memory Models
23
Patent #:
9454636
Issue Dt:
09/27/2016
Application #:
14677206
Filing Dt:
04/02/2015
Publication #:
US20160292343
Pub Dt:
10/06/2016
Title:
Integrated Circuit Design Optimization
24
Patent #:
9460254
Issue Dt:
10/04/2016
Application #:
14678697
Filing Dt:
04/03/2015
Publication #:
US20160292313
Pub Dt:
10/06/2016
Title:
Scaling Logic Components of Integrated Circuit Design
25
Patent #:
9454628
Issue Dt:
09/27/2016
Application #:
14678702
Filing Dt:
04/03/2015
Publication #:
US20160292314
Pub Dt:
10/06/2016
Title:
SCALING MEMORY COMPONENTS OF INTEGRATED CIRCUIT DESIGN
26
Patent #:
9460255
Issue Dt:
10/04/2016
Application #:
14678708
Filing Dt:
04/03/2015
Publication #:
US20160292315
Pub Dt:
10/06/2016
Title:
SCALING OF INTEGRATED CIRCUIT DESIGN INCLUDING LOGIC AND MEMORY COMPONENTS
27
Patent #:
9460256
Issue Dt:
10/04/2016
Application #:
14678711
Filing Dt:
04/03/2015
Publication #:
US20160292316
Pub Dt:
10/06/2016
Title:
INTEGRATED CIRCUIT DESIGN SCALING FOR RECOMMENDING DESIGN POINT
28
Patent #:
9460257
Issue Dt:
10/04/2016
Application #:
14678715
Filing Dt:
04/03/2015
Publication #:
US20160292317
Pub Dt:
10/06/2016
Title:
SCALING OF INTEGRATED CIRCUIT DESIGN INCLUDING HIGH-LEVEL LOGIC COMPONENTS
29
Patent #:
9984997
Issue Dt:
05/29/2018
Application #:
14810261
Filing Dt:
07/27/2015
Publication #:
US20160027482
Pub Dt:
01/28/2016
Title:
COMMUNICATION INTERFACE ARCHITECTURE USING SERIALIZER/DESERIALIZER
30
Patent #:
10018670
Issue Dt:
07/10/2018
Application #:
14963076
Filing Dt:
12/08/2015
Publication #:
US20160161554
Pub Dt:
06/09/2016
Title:
WIRELESS PROBES
31
Patent #:
10050003
Issue Dt:
08/14/2018
Application #:
14963081
Filing Dt:
12/08/2015
Publication #:
US20160163669
Pub Dt:
06/09/2016
Title:
ELONGATED PAD STRUCTURE
32
Patent #:
9711220
Issue Dt:
07/18/2017
Application #:
14963087
Filing Dt:
12/08/2015
Publication #:
US20160163385
Pub Dt:
06/09/2016
Title:
DUO CONTENT ADDRESSABLE MEMORY (CAM) USING A SINGLE CAM
33
Patent #:
NONE
Issue Dt:
Application #:
15250885
Filing Dt:
08/29/2016
Publication #:
US20160371411
Pub Dt:
12/22/2016
Title:
Scaling of Integrated Circuit Design Including High-Level Logic Components
Assignor
1
ESILICON CORPORATION
Exec Dt:
09/05/2017
Assignee
1
SILICON VALLEY BANK
3003 TASMAN DRIVE
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
SIGI HINOJOSA
1000 WILSHIRE BLVD., SUITE 1500
C/O BUCHALTER A PROFESSIONAL CORPORATION
LOS ANGELES, CA 90017-2457

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