Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 008816/0833 | |
| Pages: | 11 |
| | Recorded: | 11/10/1997 | | |
| Conveyance: | MERGER (SEE DOCUMENT FOR DETAILS). |
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Total properties:
10
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08759304
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Filing Dt:
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12/02/1996
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH TWO DIMENSIONAL MEMORY ADDRESSING
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Patent #:
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Issue Dt:
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01/19/1999
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Application #:
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08766512
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Filing Dt:
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12/13/1996
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Title:
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PROGRAMMABLE LOGIC DEVICE MACROCELL WITH IMPROVED CAPABILITY
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Patent #:
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Issue Dt:
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12/15/1998
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Application #:
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08772567
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Filing Dt:
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12/24/1996
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Title:
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SENSE AMPLIFIER WITH INDIVIDUALLY OPTIMIZED HIGH AND LOW POWER MODES
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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08807561
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Filing Dt:
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02/28/1997
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Title:
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PROGRAMMABLE LOGIC ARRAY INTEGRATED CIRCUIT ARCHITECTURES
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Patent #:
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Issue Dt:
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07/20/1999
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Application #:
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08827328
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Filing Dt:
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03/26/1997
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Title:
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TWO-TERMINAL ELECTRICALLY-REPROGRAMMABLE PROGRAMMABLE LOGIC ELEMENT
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Patent #:
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Issue Dt:
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12/15/1998
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Application #:
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08834996
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Filing Dt:
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04/07/1997
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Title:
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PROGRAMMABLE LOGIC ARRAY INTERGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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12/15/1998
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Application #:
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08834998
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Filing Dt:
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04/07/1997
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Title:
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PROGRAMMABLE LOGIC ARRAY INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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08837117
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Filing Dt:
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04/14/1997
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Title:
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SEGMENTED LOCALIZED CONDUCTORS FOR PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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10/27/1998
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Application #:
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08847004
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Filing Dt:
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05/01/1997
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Title:
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PROGRAMMABLE LOGIC ARRAY INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/27/2001
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Application #:
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08850790
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Filing Dt:
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05/02/1997
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Title:
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ELECTRONIC CIRCUIT TESTING METHODS AND APPARATUS
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Assignee
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| 101 INNOVATION DRIVE |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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C/O FISH & NEAVE
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ROBERT R. JACKSON
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50TH FLOOR
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1251 AVENUE OF THE AMERICAS
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NEW YORK, NY 10020
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