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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:024990/0837   Pages: 4
Recorded: 09/16/2010
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 11
1
Patent #:
Issue Dt:
06/10/2003
Application #:
09056555
Filing Dt:
04/07/1998
Title:
METHOD OF FORMING SEMICONDUCTOR DEVICE WITH LDD STRUCTURE
2
Patent #:
Issue Dt:
03/20/2001
Application #:
09364366
Filing Dt:
07/30/1999
Title:
METHOD OF MAKING INTEGRATED CIRCUIT CAPACITOR INCLUDING TAPERED PLUG
3
Patent #:
Issue Dt:
06/19/2001
Application #:
09364603
Filing Dt:
07/30/1999
Title:
INTEGRATED CIRCUIT CAPACITOR INCLUDING TAPERED PLUG
4
Patent #:
Issue Dt:
04/01/2003
Application #:
09481992
Filing Dt:
01/11/2000
Title:
METHOD OF MAKING A GRADED GROWN, HIGH QUALITY OXIDE LAYER FOR A SEMICONDUCTOR DEVICE
5
Patent #:
Issue Dt:
05/25/2004
Application #:
09597012
Filing Dt:
06/20/2000
Title:
SEMICONDUCTOR DEVICE FREE OF LLD REGIONS
6
Patent #:
Issue Dt:
02/10/2004
Application #:
09950384
Filing Dt:
09/10/2001
Publication #:
Pub Dt:
03/13/2003
Title:
VERTICAL REPLACEMENT-GATE JUNCTION FIELD-EFFECT TRANSISTOR
7
Patent #:
Issue Dt:
07/06/2004
Application #:
09956382
Filing Dt:
09/18/2001
Publication #:
Pub Dt:
03/20/2003
Title:
BIPOLAR JUNCTION TRANSISTOR COMPATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
8
Patent #:
Issue Dt:
02/03/2004
Application #:
09961477
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
03/27/2003
Title:
MULTIPLE OPERATING VOLTAGE VERTICAL REPLACEMENT-GATE (VRG) TRANSISTOR
9
Patent #:
Issue Dt:
03/23/2004
Application #:
09968234
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
04/03/2003
Title:
VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR
10
Patent #:
Issue Dt:
12/23/2003
Application #:
09972481
Filing Dt:
10/05/2001
Publication #:
Pub Dt:
01/02/2003
Title:
THIN FILM MULTI-LAYER HIGH Q TRANSFORMER FORMED IN A SEMICONDUCTOR SUBSTRATE
11
Patent #:
Issue Dt:
10/28/2003
Application #:
09972482
Filing Dt:
10/05/2001
Publication #:
Pub Dt:
01/02/2003
Title:
MULTI-LAYER INDUCTOR FORMED IN A SEMICONDUCTOR SUBSTRATE
Assignor
1
Exec Dt:
08/31/2002
Assignee
1
1110 AMERICAN PARKWAY NE
ALLENTOWN, PENNSYLVANIA 18109
Correspondence name and address
PATRICIA M. LOTT
400 CONNELL DRIVE
BERKELEY HEIGHTS, NJ 07922

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