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Reel/Frame:	053351/0839			Pages:	13
		Recorded:	07/16/2020
Attorney Dkt #:	TSMC-ALSEPHINA-159
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 159
Page 1 of 2
Pages: 1 2

Patent #:	6682872	Issue Dt:	01/27/2004	Application #:	10056245	Filing Dt:	01/22/2002
Publication #:	US20030138733	Pub Dt:	07/24/2003
Title:	UV-CURABLE COMPOSITIONS AND METHOD OF USE THEREOF IN MICROELECTRONICS

Patent #:	7381276	Issue Dt:	06/03/2008	Application #:	10064451	Filing Dt:	07/16/2002
Publication #:	US20040011293	Pub Dt:	01/22/2004
Title:	SUSCEPTOR POCKET WITH BEVELED PROJECTION SIDEWALL

Patent #:	7378710	Issue Dt:	05/27/2008	Application #:	10539335	Filing Dt:	06/15/2005
Publication #:	US20060068531	Pub Dt:	03/30/2006
Title:	FINFET SRAM CELL USING INVERTED FINFET THIN FILM TRANSISTORS

Patent #:	6812105	Issue Dt:	11/02/2004	Application #:	10604382	Filing Dt:	07/16/2003
Title:	ULTRA-THIN CHANNEL DEVICE WITH RAISED SOURCE AND DRAIN AND SOLID SOURCE EXTENSION DOPING

Patent #:	6803660	Issue Dt:	10/12/2004	Application #:	10627790	Filing Dt:	07/25/2003
Title:	PATTERNING LAYERS COMPRISED OF SPIN-ON CERAMIC FILMS

Patent #:	7378738	Issue Dt:	05/27/2008	Application #:	10653476	Filing Dt:	09/02/2003
Publication #:	US20050045997	Pub Dt:	03/03/2005
Title:	METHOD FOR PRODUCING SELF-ALIGNED MASK, ARTICLES PRODUCED BY SAME AND COMPOSITION FOR SAME

Patent #:	7384868	Issue Dt:	06/10/2008	Application #:	10662900	Filing Dt:	09/15/2003
Publication #:	US20050059242	Pub Dt:	03/17/2005
Title:	REDUCTION OF SILICIDE FORMATION TEMPERATURE ON SIGE CONTAINING SUBSTRATES

Patent #:	7361991	Issue Dt:	04/22/2008	Application #:	10666564	Filing Dt:	09/19/2003
Publication #:	US20050062165	Pub Dt:	03/24/2005
Title:	Closed air gap interconnect structure

Patent #:	7109099	Issue Dt:	09/19/2006	Application #:	10688047	Filing Dt:	10/17/2003
Publication #:	US20050085055	Pub Dt:	04/21/2005
Title:	END OF RANGE (EOR) SECONDARY DEFECT ENGINEERING USING SUBSTITUTIONAL CARBON DOPING

Patent #:	7187081	Issue Dt:	03/06/2007	Application #:	10699238	Filing Dt:	10/31/2003
Publication #:	US20040147111	Pub Dt:	07/29/2004
Title:	POLYCARBOSILANE BURIED ETCH STOPS IN INTERCONNECT STRUCTURES

Patent #:	7951660	Issue Dt:	05/31/2011	Application #:	10703355	Filing Dt:	11/07/2003
Publication #:	US20050098804	Pub Dt:	05/12/2005
Title:	METHODS FOR FABRICATING A METAL-OXIDE-SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	7404874	Issue Dt:	07/29/2008	Application #:	10710226	Filing Dt:	06/28/2004
Publication #:	US20050284576	Pub Dt:	12/29/2005
Title:	METHOD AND APPARATUS FOR TREATING WAFER EDGE REGION WITH TOROIDAL PLASMA

Patent #:	7390748	Issue Dt:	06/24/2008	Application #:	10710827	Filing Dt:	08/05/2004
Publication #:	US20060030154	Pub Dt:	02/09/2006
Title:	METHOD OF FORMING A POLISHING INHIBITING LAYER USING A SLURRY HAVING AN ADDITIVE

Patent #:	7253098	Issue Dt:	08/07/2007	Application #:	10711145	Filing Dt:	08/27/2004
Publication #:	US20060043590	Pub Dt:	03/02/2006
Title:	MAINTAINING UNIFORM CMP HARD MASK THICKNESS

Patent #:	7291550	Issue Dt:	11/06/2007	Application #:	10778293	Filing Dt:	02/13/2004
Publication #:	US20050181588	Pub Dt:	08/18/2005
Title:	METHOD TO FORM A CONTACT HOLE

Patent #:	7504727	Issue Dt:	03/17/2009	Application #:	10845718	Filing Dt:	05/14/2004
Publication #:	US20050258542	Pub Dt:	11/24/2005
Title:	A SEMICONDUCTOR INTERCONNECT STRUCTURE UTILIZING A POROUS DIELECTRIC MATERIAL AS AN ETCH STOP LAYER BETWEEN ADJACENT NON-POROUS DIELECTRIC MATERIALS

Patent #:	7352064	Issue Dt:	04/01/2008	Application #:	10904323	Filing Dt:	11/04/2004
Publication #:	US20060094230	Pub Dt:	05/04/2006
Title:	MULTIPLE LAYER RESIST SCHEME IMPLEMENTING ETCH RECIPE PARTICULAR TO EACH LAYER

Patent #:	7476926	Issue Dt:	01/13/2009	Application #:	10905475	Filing Dt:	01/06/2005
Publication #:	US20060145235	Pub Dt:	07/06/2006
Title:	ERASABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE

Patent #:	7405152	Issue Dt:	07/29/2008	Application #:	10906013	Filing Dt:	01/31/2005
Publication #:	US20060172514	Pub Dt:	08/03/2006
Title:	REDUCING WIRE EROSION DURING DAMASCENE PROCESSING

Patent #:	7354867	Issue Dt:	04/08/2008	Application #:	10906112	Filing Dt:	02/03/2005
Publication #:	US20060172535	Pub Dt:	08/03/2006
Title:	ETCH PROCESS FOR IMPROVING YIELD OF DIELECTRIC CONTACTS ON NICKEL SILICIDES

Patent #:	7355221	Issue Dt:	04/08/2008	Application #:	10908448	Filing Dt:	05/12/2005
Publication #:	US20060255415	Pub Dt:	11/16/2006
Title:	FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRICALLY STRESSED CHANNEL REGION

Patent #:	8118535	Issue Dt:	02/21/2012	Application #:	10908594	Filing Dt:	05/18/2005
Publication #:	US20060263197	Pub Dt:	11/23/2006
Title:	POD SWAPPING INTERNAL TO TOOL RUN TIME

Patent #:	7268048	Issue Dt:	09/11/2007	Application #:	10913214	Filing Dt:	08/06/2004
Publication #:	US20060030095	Pub Dt:	02/09/2006
Title:	METHODS FOR ELIMINATION OF ARSENIC BASED DEFECTS IN SEMICONDUCTOR DEVICES WITH ISOLATION REGIONS

Patent #:	7271446	Issue Dt:	09/18/2007	Application #:	10916814	Filing Dt:	08/12/2004
Publication #:	US20050014314	Pub Dt:	01/20/2005
Title:	ULTRA-THIN CHANNEL DEVICE WITH RAISED SOURCE AND DRAIN AND SOLID SOURCE EXTENSION DOPING

Patent #:	7268066	Issue Dt:	09/11/2007	Application #:	10922093	Filing Dt:	08/19/2004
Publication #:	US20050020019	Pub Dt:	01/27/2005
Title:	METHOD FOR SEMICONDUCTOR GATE LINE DIMENSION REDUCTION

Patent #:	7544610	Issue Dt:	06/09/2009	Application #:	10935497	Filing Dt:	09/07/2004
Publication #:	US20060051961	Pub Dt:	03/09/2006
Title:	METHOD AND PROCESS FOR FORMING A SELF-ALIGNED SILICIDE CONTACT

Patent #:	7329439	Issue Dt:	02/12/2008	Application #:	10953752	Filing Dt:	09/29/2004
Publication #:	US20060069177	Pub Dt:	03/30/2006
Title:	UV-CURABLE SOLVENT FREE COMPOSITIONS AND USE THEREOF IN CERAMIC CHIP DEFECT REPAIR

Patent #:	7332436	Issue Dt:	02/19/2008	Application #:	10966301	Filing Dt:	10/15/2004
Publication #:	US20050224748	Pub Dt:	10/13/2005
Title:	PROCESS OF REMOVING RESIDUE FROM A PRECISION SURFACE USING LIQUID OR SUPERCRITICAL CARBON DIOXIDE COMPOSITION

Patent #:	7387911	Issue Dt:	06/17/2008	Application #:	10990778	Filing Dt:	11/16/2004
Publication #:	US20060105547	Pub Dt:	05/18/2006
Title:	APPLICATION OF A THERMALLY CONDUCTIVE THIN FILM TO A WAFER BACKSIDE PRIOR TO DICING TO PREVENT CHIPPING AND CRACKING

Patent #:	7271110	Issue Dt:	09/18/2007	Application #:	11029835	Filing Dt:	01/05/2005
Publication #:	US20060148270	Pub Dt:	07/06/2006
Title:	HIGH DENSITY PLASMA AND BIAS RF POWER PROCESS TO MAKE STABLE FSG WITH LESS FREE F AND SIN WITH LESS H TO ENHANCE THE FSG/SIN INTEGRATION RELIABILITY

Patent #:	7297640	Issue Dt:	11/20/2007	Application #:	11034952	Filing Dt:	01/13/2005
Publication #:	US20060154491	Pub Dt:	07/13/2006
Title:	METHOD FOR REDUCING ARGON DIFFUSION FROM HIGH DENSITY PLASMA FILMS

Patent #:	7256112	Issue Dt:	08/14/2007	Application #:	11039429	Filing Dt:	01/20/2005
Publication #:	US20060160343	Pub Dt:	07/20/2006
Title:	LASER ACTIVATION OF IMPLANTED CONTACT PLUG FOR MEMORY BITLINE FABRICATION

Patent #:	7452568	Issue Dt:	11/18/2008	Application #:	11049846	Filing Dt:	02/04/2005
Publication #:	US20060177568	Pub Dt:	08/10/2006
Title:	CENTRIFUGAL METHOD FOR FILING HIGH ASPECT RATIO BLIND MICRO VIAS WITH POWDERED MATERIALS FOR CIRCUIT FORMATION

Patent #:	7381637	Issue Dt:	06/03/2008	Application #:	11053706	Filing Dt:	02/08/2005
Publication #:	US20050146040	Pub Dt:	07/07/2005
Title:	METAL SPACER IN SINGLE AND DUAL DAMASCENE PROCESSING

Patent #:	7326983	Issue Dt:	02/05/2008	Application #:	11082993	Filing Dt:	03/17/2005
Publication #:	US20050164468	Pub Dt:	07/28/2005
Title:	SELECTIVE SILICON-ON-INSULATOR ISOLATION STRUCTURE AND METHOD

Patent #:	7348611	Issue Dt:	03/25/2008	Application #:	11112820	Filing Dt:	04/22/2005
Publication #:	US20060237785	Pub Dt:	10/26/2006
Title:	STRAINED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ON ROTATED WAFERS AND METHODS THEREOF

Patent #:	7256084	Issue Dt:	08/14/2007	Application #:	11122667	Filing Dt:	05/04/2005
Publication #:	US20060252194	Pub Dt:	11/09/2006
Title:	COMPOSITE STRESS SPACER

Patent #:	7247363	Issue Dt:	07/24/2007	Application #:	11137957	Filing Dt:	05/26/2005
Publication #:	US20050214508	Pub Dt:	09/29/2005
Title:	SUPPORTED GREENSHEET STRUCTURE AND METHOD IN MLC PROCESSING

Patent #:	7253097	Issue Dt:	08/07/2007	Application #:	11160624	Filing Dt:	06/30/2005
Publication #:	US20070001303	Pub Dt:	01/04/2007
Title:	INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS

Patent #:	7456115	Issue Dt:	11/25/2008	Application #:	11160700	Filing Dt:	07/06/2005
Publication #:	US20070010050	Pub Dt:	01/11/2007
Title:	METHOD FOR FORMING SEMICONDUCTOR DEVICES HAVING REDUCED GATE EDGE LEAKAGE CURRENT

Patent #:	7384878	Issue Dt:	06/10/2008	Application #:	11161214	Filing Dt:	07/27/2005
Publication #:	US20060003468	Pub Dt:	01/05/2006
Title:	METHOD FOR APPLYING A LAYER TO A HYDROPHOBIC SURFACE

Patent #:	7459367	Issue Dt:	12/02/2008	Application #:	11161239	Filing Dt:	07/27/2005
Publication #:	US20070023811	Pub Dt:	02/01/2007
Title:	METHOD OF FORMING A VERTICAL P-N JUNCTION DEVICE

Patent #:	7382029	Issue Dt:	06/03/2008	Application #:	11161337	Filing Dt:	07/29/2005
Publication #:	US20070026598	Pub Dt:	02/01/2007
Title:	METHOD AND APPARATUS FOR IMPROVING INTEGRATED CIRCUIT DEVICE PERFORMANCE USING HYBRID CRYSTAL ORIENTATIONS

Patent #:	7381646	Issue Dt:	06/03/2008	Application #:	11161722	Filing Dt:	08/15/2005
Publication #:	US20070037394	Pub Dt:	02/15/2007
Title:	A METHOD FOR USING A CU BEOL PROCESS TO FABRICATE AN INTEGRATED CIRCUIT (IC) ORIGINALLY HAVING AN AL DESIGN

Patent #:	8299500	Issue Dt:	10/30/2012	Application #:	11161936	Filing Dt:	08/23/2005
Publication #:	US20070051980	Pub Dt:	03/08/2007
Title:	SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR HAVING INTERSTITIAL TRAPPING LAYER IN BASE REGION

Patent #:	7442585	Issue Dt:	10/28/2008	Application #:	11162126	Filing Dt:	08/30/2005
Publication #:	US20070045611	Pub Dt:	03/01/2007
Title:	MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME

Patent #:	7394154	Issue Dt:	07/01/2008	Application #:	11162513	Filing Dt:	09/13/2005
Publication #:	US20070057374	Pub Dt:	03/15/2007
Title:	EMBEDDED BARRIER FOR DIELECTRIC ENCAPSULATION

Patent #:	7335563	Issue Dt:	02/26/2008	Application #:	11164070	Filing Dt:	11/09/2005
Publication #:	US20070105326	Pub Dt:	05/10/2007
Title:	ROTATED FIELD EFFECT TRANSISTORS AND METHOD OF MANUFACTURE

Patent #:	7419907	Issue Dt:	09/02/2008	Application #:	11173038	Filing Dt:	07/01/2005
Publication #:	US20070004205	Pub Dt:	01/04/2007
Title:	ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS NI ALLOY SILICIDE STRUCTURE

Patent #:	7994575	Issue Dt:	08/09/2011	Application #:	11175582	Filing Dt:	07/06/2005
Publication #:	US20050242378	Pub Dt:	11/03/2005
Title:	METAL-OXIDE-SEMICONDUCTOR DEVICE STRUCTURES WITH TAILORED DOPANT DEPTH PROFILES

Patent #:	7445945	Issue Dt:	11/04/2008	Application #:	11194843	Filing Dt:	08/01/2005
Title:	METHOD AND APPARATUS FOR DYNAMIC ADJUSTMENT OF A SAMPLING PLAN BASED ON WAFER ELECTRICAL TEST DATA

Patent #:	7420248	Issue Dt:	09/02/2008	Application #:	11211813	Filing Dt:	08/25/2005
Publication #:	US20070045733	Pub Dt:	03/01/2007
Title:	PROGRAMMABLE RANDOM LOGIC ARRAYS USING PN ISOLATION

Patent #:	7381655	Issue Dt:	06/03/2008	Application #:	11226726	Filing Dt:	09/14/2005
Publication #:	US20070059891	Pub Dt:	03/15/2007
Title:	MANDREL/TRIM ALIGNMENT IN SIT PROCESSING

Patent #:	7326601	Issue Dt:	02/05/2008	Application #:	11235791	Filing Dt:	09/26/2005
Publication #:	US20070072380	Pub Dt:	03/29/2007
Title:	METHODS FOR FABRICATION OF A STRESSED MOS DEVICE

Patent #:	7348216	Issue Dt:	03/25/2008	Application #:	11243882	Filing Dt:	10/04/2005
Publication #:	US20070077752	Pub Dt:	04/05/2007
Title:	REWORK PROCESS FOR REMOVING RESIDUAL UV ADHESIVE FROM C4 WAFER SURFACES

Patent #:	7476552	Issue Dt:	01/13/2009	Application #:	11247369	Filing Dt:	10/11/2005
Publication #:	US20060194349	Pub Dt:	08/31/2006
Title:	METHOD OF REWORKING A SEMICONDUCTOR STRUCTURE

Patent #:	7541679	Issue Dt:	06/02/2009	Application #:	11247818	Filing Dt:	10/11/2005
Publication #:	US20060027929	Pub Dt:	02/09/2006
Title:	EXPOSED PORE SEALING POST PATTERNING

Patent #:	7442996	Issue Dt:	10/28/2008	Application #:	11275644	Filing Dt:	01/20/2006
Publication #:	US20070170515	Pub Dt:	07/26/2007
Title:	STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS

Patent #:	7303968	Issue Dt:	12/04/2007	Application #:	11299682	Filing Dt:	12/13/2005
Publication #:	US20060157824	Pub Dt:	07/20/2006
Title:	SEMICONDUCTOR DEVICE AND METHOD HAVING MULTIPLE SUBCOLLECTORS FORMED ON A COMMON WAFER

Patent #:	7504696	Issue Dt:	03/17/2009	Application #:	11306748	Filing Dt:	01/10/2006
Publication #:	US20070278590	Pub Dt:	12/06/2007
Title:	CMOS WITH DUAL METAL GATE

Patent #:	7368393	Issue Dt:	05/06/2008	Application #:	11308672	Filing Dt:	04/20/2006
Publication #:	US20070246442	Pub Dt:	10/25/2007
Title:	CHEMICAL OXIDE REMOVAL OF PLASMA DAMAGED SICOH LOW K DIELECTRICS

Patent #:	7374998	Issue Dt:	05/20/2008	Application #:	11346662	Filing Dt:	02/03/2006
Publication #:	US20070184619	Pub Dt:	08/09/2007
Title:	SELECTIVE INCORPORATION OF CHARGE FOR TRANSISTOR CHANNELS

Patent #:	7257502	Issue Dt:	08/14/2007	Application #:	11363748	Filing Dt:	02/28/2006
Title:	DETERMINING METROLOGY SAMPLING DECISIONS BASED ON FABRICATION SIMULATION

Patent #:	7242071	Issue Dt:	07/10/2007	Application #:	11382720	Filing Dt:	07/06/2006
Title:	SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE

Patent #:	7442619	Issue Dt:	10/28/2008	Application #:	11383965	Filing Dt:	05/18/2006
Publication #:	US20070267753	Pub Dt:	11/22/2007
Title:	METHOD OF FORMING SUBSTANTIALLY L-SHAPED SILICIDE CONTACT FOR A SEMICONDUCTOR DEVICE

Patent #:	7396407	Issue Dt:	07/08/2008	Application #:	11406123	Filing Dt:	04/18/2006
Publication #:	US20070241323	Pub Dt:	10/18/2007
Title:	TRENCH-EDGE-DEFECT-FREE RECRYSTALLIZATION BY EDGE-ANGLE-OPTIMIZED SOLID PHASE EPITAXY: METHOD AND APPLICATIONS TO HYBRID ORIENTATION SUBSTRATES

Patent #:	7410852	Issue Dt:	08/12/2008	Application #:	11408522	Filing Dt:	04/21/2006
Publication #:	US20070249131	Pub Dt:	10/25/2007
Title:	OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE FIELD EFFECT TRANSISTORS

Patent #:	7491555	Issue Dt:	02/17/2009	Application #:	11419782	Filing Dt:	05/23/2006
Publication #:	US20070048883	Pub Dt:	03/01/2007
Title:	METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING THE FABRICATION OF INTERCONNECT STRUCTURES AND CONTACTS IN A SEMICONDUCTOR DEVICE

Patent #:	7504326	Issue Dt:	03/17/2009	Application #:	11420819	Filing Dt:	05/30/2006
Publication #:	US20070281450	Pub Dt:	12/06/2007
Title:	USE OF SCANNING THEME IMPLANTERS AND ANNEALERS FOR SELECTIVE IMPLANTATION AND ANNEALING

Patent #:	7378338	Issue Dt:	05/27/2008	Application #:	11461220	Filing Dt:	07/31/2006
Publication #:	US20060264048	Pub Dt:	11/23/2006
Title:	A METHOD OF FORMING AN INTERCONNECT STRUCTURE DIFFUSION BARRIER WITH HIGH NITROGEN CONTENT

Patent #:	7482697	Issue Dt:	01/27/2009	Application #:	11461960	Filing Dt:	08/02/2006
Publication #:	US20080029904	Pub Dt:	02/07/2008
Title:	DOUBLE-SIDED WAFFLE PACK

Patent #:	7400018	Issue Dt:	07/15/2008	Application #:	11462846	Filing Dt:	08/07/2006
Publication #:	US20060270168	Pub Dt:	11/30/2006
Title:	END OF RANGE (EOR) SECONDARY DEFECT ENGINEERING USING CHEMICAL VAPOR DEPOSITION (CVD) SUBSTITUTIONAL CARBON DOPING

Patent #:	7316940	Issue Dt:	01/08/2008	Application #:	11463348	Filing Dt:	08/09/2006
Publication #:	US20060292830	Pub Dt:	12/28/2006
Title:	CHIP DICING

Patent #:	7436030	Issue Dt:	10/14/2008	Application #:	11463640	Filing Dt:	08/10/2006
Publication #:	US20080036012	Pub Dt:	02/14/2008
Title:	STRAINED MOSFETS ON SEPARATED SILICON LAYERS

Patent #:	7416986	Issue Dt:	08/26/2008	Application #:	11469940	Filing Dt:	09/05/2006
Publication #:	US20080057667	Pub Dt:	03/06/2008
Title:	TEST STRUCTURE AND METHOD FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS

Patent #:	7410874	Issue Dt:	08/12/2008	Application #:	11481213	Filing Dt:	07/05/2006
Publication #:	US20080124872	Pub Dt:	05/29/2008
Title:	METHOD OF INTEGRATING TRIPLE GATE OXIDE THICKNESS

Patent #:	8125019	Issue Dt:	02/28/2012	Application #:	11550450	Filing Dt:	10/18/2006
Publication #:	US20080093659	Pub Dt:	04/24/2008
Title:	ELECTRICALLY PROGRAMMABLE RESISTOR

Patent #:	7425278	Issue Dt:	09/16/2008	Application #:	11563858	Filing Dt:	11/28/2006
Publication #:	US20080124939	Pub Dt:	05/29/2008
Title:	PROCESS OF ETCHING A TITANIUM/TUNGSTEN SURFACE AND ETCHANT USED THEREIN

Patent #:	8053327	Issue Dt:	11/08/2011	Application #:	11614961	Filing Dt:	12/21/2006
Publication #:	US20080150074	Pub Dt:	06/26/2008
Title:	METHOD OF MANUFACTURE OF AN INTEGRATED CIRCUIT SYSTEM WITH SELF-ALIGNED ISOLATION STRUCTURES

Patent #:	7538339	Issue Dt:	05/26/2009	Application #:	11615153	Filing Dt:	12/22/2006
Publication #:	US20080150033	Pub Dt:	06/26/2008
Title:	SCALABLE STRAINED FET DEVICE AND METHOD OF FABRICATING THE SAME

Patent #:	7521776	Issue Dt:	04/21/2009	Application #:	11618346	Filing Dt:	12/29/2006
Publication #:	US20080157202	Pub Dt:	07/03/2008
Title:	SOFT ERROR REDUCTION OF CMOS CIRCUITS ON SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION USING BURIED RECOMBINATION CENTERS

Patent #:	7396758	Issue Dt:	07/08/2008	Application #:	11619502	Filing Dt:	01/03/2007
Publication #:	US20070111509	Pub Dt:	05/17/2007
Title:	POLYCARBOSILANE BURIED ETCH STOPS IN INTERCONNECT STRUCTURES

Patent #:	7485508	Issue Dt:	02/03/2009	Application #:	11627653	Filing Dt:	01/26/2007
Publication #:	US20080179678	Pub Dt:	07/31/2008
Title:	TWO-SIDED SEMICONDUCTOR-ON-INSULATOR STRUCTURES AND METHODS OF MANUFACTURING THE SAME

Patent #:	7544609	Issue Dt:	06/09/2009	Application #:	11673276	Filing Dt:	02/09/2007
Publication #:	US20080194099	Pub Dt:	08/14/2008
Title:	METHOD FOR INTEGRATING LINER FORMATION IN BACK END OF LINE PROCESSING

Patent #:	7498208	Issue Dt:	03/03/2009	Application #:	11689549	Filing Dt:	03/22/2007
Publication #:	US20070184602	Pub Dt:	08/09/2007
Title:	CHEVRON CMOS TRIGATE STRUCTURE

Patent #:	9460924	Issue Dt:	10/04/2016	Application #:	11691332	Filing Dt:	03/26/2007
Publication #:	US20080237803	Pub Dt:	10/02/2008
Title:	SEMICONDUCTOR DEVICE HAVING STRUCTURE WITH FRACTIONAL DIMENSION OF THE MINIMUM DIMENSION OF A LITHOGRAPHY SYSTEM

Patent #:	7528451	Issue Dt:	05/05/2009	Application #:	11692402	Filing Dt:	03/28/2007
Publication #:	US20080237749	Pub Dt:	10/02/2008
Title:	CMOS GATE CONDUCTOR HAVING CROSS-DIFFUSION BARRIER

Patent #:	7550396	Issue Dt:	06/23/2009	Application #:	11742878	Filing Dt:	05/01/2007
Publication #:	US20080081480	Pub Dt:	04/03/2008
Title:	METHOD FOR REDUCING RESIST POISONING DURING PATTERNING OF SILICON NITRIDE LAYERS IN A SEMICONDUCTOR DEVICE

Patent #:	7504311	Issue Dt:	03/17/2009	Application #:	11762376	Filing Dt:	06/13/2007
Publication #:	US20070228484	Pub Dt:	10/04/2007
Title:	STRUCTURE AND METHOD OF INTEGRATING COMPOUND AND ELEMENTAL SEMICONDUCTORS FOR HIGH-PERFORMANCE CMOS

Patent #:	8101512	Issue Dt:	01/24/2012	Application #:	11773631	Filing Dt:	07/05/2007
Publication #:	US20080026552	Pub Dt:	01/31/2008
Title:	METHOD OF ENHANCING LITHOGRAPHY CAPABILITIES DURING GATE FORMATION IN SEMICONDUCTORS HAVING A PRONOUNCED SURFACE TOPOGRAPHY

Patent #:	8159030	Issue Dt:	04/17/2012	Application #:	11775619	Filing Dt:	07/10/2007
Publication #:	US20080012018	Pub Dt:	01/17/2008
Title:	STRAINED MOS DEVICE AND METHODS FOR ITS FABRICATION

Patent #:	9640666	Issue Dt:	05/02/2017	Application #:	11781664	Filing Dt:	07/23/2007
Publication #:	US20090026545	Pub Dt:	01/29/2009
Title:	INTEGRATED CIRCUIT EMPLOYING VARIABLE THICKNESS FILM

Patent #:	9093481	Issue Dt:	07/28/2015	Application #:	11789157	Filing Dt:	04/23/2007
Publication #:	US20080257383	Pub Dt:	10/23/2008
Title:	Method for semiconductor wafer fabrication utilizing a cleaning substrate

Patent #:	7854202	Issue Dt:	12/21/2010	Application #:	11828657	Filing Dt:	07/26/2007
Publication #:	US20090025598	Pub Dt:	01/29/2009
Title:	OVERHEAD TRANSPORT SERVICE VEHICLE AND METHOD

Patent #:	8465657	Issue Dt:	06/18/2013	Application #:	11833283	Filing Dt:	08/03/2007
Publication #:	US20070267386	Pub Dt:	11/22/2007
Title:	POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY

Patent #:	7491623	Issue Dt:	02/17/2009	Application #:	11841018	Filing Dt:	08/20/2007
Publication #:	US20080057673	Pub Dt:	03/06/2008
Title:	METHOD OF MAKING A SEMICONDUCTOR STRUCTURE

Patent #:	7514361	Issue Dt:	04/07/2009	Application #:	11841114	Filing Dt:	08/20/2007
Publication #:	US20090053890	Pub Dt:	02/26/2009
Title:	SELECTIVE THIN METAL CAP PROCESS

Patent #:	8394724	Issue Dt:	03/12/2013	Application #:	11843629	Filing Dt:	08/22/2007
Publication #:	US20080054477	Pub Dt:	03/06/2008
Title:	PROCESSING WITH REDUCED LINE END SHORTENING RATIO

Patent #:	7633103	Issue Dt:	12/15/2009	Application #:	11846318	Filing Dt:	08/28/2007
Publication #:	US20090057729	Pub Dt:	03/05/2009
Title:	SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME

100

Patent #:	7972965	Issue Dt:	07/05/2011	Application #:	11862706	Filing Dt:	09/27/2007
Publication #:	US20080020546	Pub Dt:	01/24/2008
Title:	PROCESS FOR INTERFACIAL ADHESION IN LAMINATE STRUCTURES THROUGH PATTERNED ROUGHING OF A SURFACE

Assignor

ALSEPHINA INNOVATIONS, INC.

Exec Dt:

02/11/2020

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

NO.8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK,

HSINCHU, TAIWAN 30078

Correspondence name and address
	JCIPRNET
	8F-1, NO. 100, ROOSEVELT RD. SEC. 2,
	HSINCHU, 100404 TAIWAN

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