Total properties:
30
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Patent #:
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Issue Dt:
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08/10/1993
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Application #:
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07869683
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Filing Dt:
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04/15/1992
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Title:
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DYNAMIC RANDOM ACCESS MEMORY CELL HAVING A STACKED-TRENCH CAPACITOR THAT IS RESISTANT TO ALPHA PARTICLE GENERATED SOFT ERRORS, AND METHOD OF MANUFACTURING SAME
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Patent #:
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Issue Dt:
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05/13/1997
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Application #:
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08509782
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Filing Dt:
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08/01/1995
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Title:
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SEMICONDUCTOR PROCESSING METHOD OF FORMING FIELD OXIDE REGIONS ON A SEMICONDUCTOR SUBSTRATE UTILIZING A LATERALLY OUTWARD PROJECTING FOOT PORTION
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Patent #:
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Issue Dt:
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08/26/1997
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Application #:
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08514159
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Filing Dt:
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08/11/1995
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Title:
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METHOD FOR FORMING FIELD OXIDE HAVING UNIFORM THICKNESS
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Patent #:
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Issue Dt:
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04/14/1998
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Application #:
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08539855
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Filing Dt:
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10/06/1995
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Title:
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INTEGRATED CHIP MULTILAYER DECOUPLING CAPACITORS
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Patent #:
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Issue Dt:
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08/05/1997
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Application #:
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08590313
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Filing Dt:
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01/23/1996
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Title:
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METHOD FOR LOCAL OXIDATION OF SILICON (LOCOS)FIELD ISOLATION
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Patent #:
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Issue Dt:
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05/11/1999
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Application #:
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08604219
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Filing Dt:
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02/20/1996
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Title:
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INTEGRATED CIRCUIT DEVICE HAVING CYANATE ESTER BUFFER COAT
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Patent #:
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Issue Dt:
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05/26/1998
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Application #:
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08607801
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Filing Dt:
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02/27/1996
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Title:
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MODIFIED LOCOS PROCESS FOR SUB-HALF-MICRON TECHNOLOGY
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Patent #:
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Issue Dt:
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03/02/1999
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Application #:
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08710370
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Filing Dt:
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09/16/1996
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Title:
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METHOD FOR ELECTROCHEMICAL LOCAL OXIDATION OF SILICON
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08723263
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Filing Dt:
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09/30/1996
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Title:
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REDUCED RC DELAY BETWEEN ADJACENT SUBSTRATE WIRING LINES
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Patent #:
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Issue Dt:
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07/07/1998
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Application #:
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08724319
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Filing Dt:
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10/01/1996
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Title:
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REDUCED RC DELAY BETWEEN ADJACENT SUBSTRATE WIRING LINES
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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08801811
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Filing Dt:
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02/14/1997
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Title:
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METHOD MAKING INTRGRATED CIRCUIT METALLIZATION WITH SUPERCONDUCTOR BEOL WIRING
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Patent #:
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Issue Dt:
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02/24/1998
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Application #:
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08802164
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Filing Dt:
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02/13/1997
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Title:
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NMOS FIELD EFFECT TRANSISTORS AND METHODS OF FORMING NMOS FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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08902763
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Filing Dt:
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07/30/1997
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Title:
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NMOS FIELD EFFECT TRANSISTORS AND METHODS OF FORMING NMOS FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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08906409
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Filing Dt:
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08/05/1997
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Title:
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METHOD FOR LOCAL OXIDATION OF SILICON (LOCOS) FIELD ISOLATION
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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08919849
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Filing Dt:
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08/28/1997
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Title:
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INTEGRATED CHIP MULTILAYER DECOUPLING CAPACITORS
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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08931093
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Filing Dt:
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08/20/1997
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Title:
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ASSISTED LOCAL OXIDATION OF SILICON
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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08953910
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Filing Dt:
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10/20/1997
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Title:
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METHODS OF FORMING CONDUCTIVE COMPONENTS AND METHODS OF FORMING CONDUCTIVE LINES
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09024234
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Filing Dt:
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02/17/1998
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Title:
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INTEGRATED CIRCUIT METALLIZATION WITH SUPERCONDUCTOR BEOL WIRING
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09145107
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Filing Dt:
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09/02/1998
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Title:
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VARIABLE TEMPERATURE LOCOS PROCESS
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09207890
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Filing Dt:
|
12/08/1998
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Title:
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REDUCED RC DELAY BETWEEN ADJACENT SUBSTRATE WIRING LINES
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09245999
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Filing Dt:
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02/05/1999
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Title:
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METHOD FOR ELECTROCHEMICAL OXIDATION OF SILICON
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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09257402
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Filing Dt:
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02/25/1999
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Title:
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METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE HAVING CYANATE ESTER BUFFER COAT
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09385698
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Filing Dt:
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08/30/1999
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Title:
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METHOD OF FORMING FIELD OXIDE
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09387661
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Filing Dt:
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08/30/1999
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Title:
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LOCOS PROCESSES
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09459131
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Filing Dt:
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12/10/1999
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Title:
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INTEGRATED CHIP MULTIPLAYER DECOUPLING CAPACITORS
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09515519
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Filing Dt:
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02/29/2000
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Title:
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Reduced rc delay between adjacent substrate wiring lines
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09552738
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Filing Dt:
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04/19/2000
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Title:
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METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE HAVING CYANATE ESTER BUFFER COAT
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09560704
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Filing Dt:
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04/27/2000
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Title:
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LOCOS fabrication processes and semiconductive material structures
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10156515
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Filing Dt:
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05/28/2002
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Publication #:
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Pub Dt:
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09/26/2002
| | | | |
Title:
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REDUCED RC DELAY BETWEEN ADJACENT SUBSTRATE WIRING LINES
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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10196458
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Filing Dt:
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07/16/2002
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Publication #:
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Pub Dt:
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12/26/2002
| | | | |
Title:
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INTEGRATED CIRCUIT DEVICE HAVING CYANATE ESTER BUFFER COAT AND METHOD OF FABRICATING SAME
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