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Patent #:
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Issue Dt:
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05/07/2013
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Application #:
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12997993
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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04/21/2011
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Title:
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FAULT MANAGEMENT FOR A COMMUNICATION BUS
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Patent #:
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Issue Dt:
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08/12/2014
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Application #:
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13003311
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Filing Dt:
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01/10/2011
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Publication #:
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Pub Dt:
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05/19/2011
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Title:
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METHOD AND APPARATUS FOR DETECTING ONE OR MORE PREDETERMINED TONES TRANSMITTED OVER A COMMUNICATION NETWORK
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Patent #:
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Issue Dt:
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04/02/2013
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Application #:
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13005240
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Filing Dt:
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01/12/2011
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Publication #:
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Pub Dt:
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07/12/2012
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Title:
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DEVICE HAVING CONDUCTIVE SUBSTRATE VIA WITH CATCH-PAD ETCH-STOP
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Patent #:
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Issue Dt:
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08/27/2013
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Application #:
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13010790
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Filing Dt:
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01/21/2011
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Publication #:
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Pub Dt:
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07/26/2012
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Title:
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METHOD OF TESTING ASYNCHRONOUS MODULES IN SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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13012643
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Filing Dt:
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01/24/2011
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Publication #:
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Pub Dt:
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07/26/2012
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Title:
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MEMS SENSOR WITH FOLDED TORSION SPRINGS
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Patent #:
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Issue Dt:
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09/24/2013
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Application #:
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13012671
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Filing Dt:
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01/24/2011
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Publication #:
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Pub Dt:
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07/26/2012
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Title:
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MEMS SENSOR WITH DUAL PROOF MASSES
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Patent #:
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Issue Dt:
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11/19/2013
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Application #:
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13013337
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Filing Dt:
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01/25/2011
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Publication #:
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Pub Dt:
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05/19/2011
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Title:
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PROGRAM TRACE MESSAGE GENERATION FOR PAGE CROSSING EVENTS FOR DEBUG
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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13013660
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Filing Dt:
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01/25/2011
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Publication #:
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Pub Dt:
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07/26/2012
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Title:
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METHOD AND APPARATUS FOR PROCESSING TEMPORAL AND SPATIAL OVERLAPPING UPDATES FOR AN ELECTRONIC DISPLAY
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Patent #:
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Issue Dt:
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02/26/2013
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Application #:
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13014029
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Filing Dt:
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01/26/2011
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Publication #:
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Pub Dt:
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07/26/2012
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Title:
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BIPOLAR TRANSISTOR WITH TWO DIFFERENT EMITTER PORTIONS HAVING SAME TYPE DOPANT OF DIFFERENT CONCENTRATIONS FOR IMPROVED GAIN
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Patent #:
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Issue Dt:
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12/02/2014
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Application #:
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13016327
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Filing Dt:
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01/28/2011
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Publication #:
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Pub Dt:
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08/02/2012
| | | | |
Title:
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SELECTIVE CACHE ACCESS CONTROL APPARATUS AND METHOD THEREOF
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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13016371
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Filing Dt:
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01/28/2011
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Publication #:
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Pub Dt:
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08/02/2012
| | | | |
Title:
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SELECTIVE MEMORY ACCESS TO DIFFERENT LOCAL MEMORY PORTS AND METHOD THEREOF
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Patent #:
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Issue Dt:
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04/29/2014
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Application #:
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13020565
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Filing Dt:
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02/03/2011
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Publication #:
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Pub Dt:
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08/09/2012
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Title:
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ELECTRONIC CIRCUIT HAVING SHARED LEAKAGE CURRENT REDUCTION CIRCUITS
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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13023942
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Filing Dt:
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02/09/2011
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Publication #:
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Pub Dt:
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08/09/2012
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Title:
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BIPOLAR TRANSISTOR AND METHOD WITH RECESSED BASE ELECTRODE
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Patent #:
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Issue Dt:
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04/30/2013
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Application #:
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13025135
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Filing Dt:
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02/10/2011
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Publication #:
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Pub Dt:
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08/16/2012
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Title:
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METHOD AND SYSTEM FOR DETECTING RETRANSMISSION THRESHOLD CONDITION IN SELECTIVE REPEAT ARQ COMMUNICATION SYSTEM
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Patent #:
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Issue Dt:
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12/03/2013
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Application #:
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13025201
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Filing Dt:
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02/11/2011
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Publication #:
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Pub Dt:
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08/16/2012
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Title:
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PHASE-SHIFTED PULSE WIDTH MODULATION SIGNAL GENERATION DEVICE AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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11/05/2013
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Application #:
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13025350
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Filing Dt:
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02/11/2011
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Publication #:
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Pub Dt:
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08/16/2012
| | | | |
Title:
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NEAR ZERO CHANNEL LENGTH FIELD DRIFT LDMOS
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13028930
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Filing Dt:
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02/16/2011
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Publication #:
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Pub Dt:
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08/16/2012
| | | | |
Title:
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MEMS DEVICE HAVING VARIABLE GAP WIDTH AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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02/24/2015
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Application #:
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13032107
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Filing Dt:
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02/22/2011
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Publication #:
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Pub Dt:
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08/23/2012
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Title:
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MAGNETOMETER TEST ARRANGEMENT AND METHOD
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Patent #:
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Issue Dt:
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08/25/2015
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Application #:
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13033327
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Filing Dt:
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02/23/2011
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Publication #:
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Pub Dt:
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08/23/2012
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Title:
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REMOTE PERMISSIONS PROVISIONING FOR STORAGE IN A CACHE AND DEVICE THEREFOR
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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13033854
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Filing Dt:
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02/24/2011
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Publication #:
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Pub Dt:
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08/30/2012
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Title:
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MEMS Device With Enhanced Resistance to Stiction
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Patent #:
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Issue Dt:
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03/03/2015
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Application #:
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13036251
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Filing Dt:
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02/28/2011
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Publication #:
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Pub Dt:
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08/30/2012
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Title:
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MICROPROCESSOR SYSTEMS AND METHODS FOR LATENCY TOLERANCE EXECUTION
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13036461
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Filing Dt:
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02/28/2011
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Publication #:
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Pub Dt:
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08/30/2012
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Title:
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VIAS BETWEEN CONDUCTIVE LAYERS TO IMPROVE RELIABILITY
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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13037013
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Filing Dt:
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02/28/2011
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Publication #:
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Pub Dt:
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08/30/2012
| | | | |
Title:
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SYSTEMS AND METHODS FOR CONFIGURING LOAD/STORE EXECUTION UNITS
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Patent #:
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Issue Dt:
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07/08/2014
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Application #:
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13038054
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Filing Dt:
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03/01/2011
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Publication #:
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Pub Dt:
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09/06/2012
| | | | |
Title:
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READ STACKING FOR DATA PROCESSOR INTERFACE
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Patent #:
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Issue Dt:
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12/30/2014
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Application #:
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13043075
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Filing Dt:
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03/08/2011
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Publication #:
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Pub Dt:
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09/13/2012
| | | | |
Title:
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SYSTEMS AND METHODS FOR DETECTING SURFACE CHARGE
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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13045294
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Filing Dt:
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03/10/2011
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Publication #:
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Pub Dt:
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09/13/2012
| | | | |
Title:
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MEMORY VOLTAGE REGULATOR WITH LEAKAGE CURRENT VOLTAGE CONTROL
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13045307
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Filing Dt:
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03/10/2011
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Publication #:
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Pub Dt:
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09/13/2012
| | | | |
Title:
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HIERARCHICAL ERROR CORRECTION FOR LARGE MEMORIES
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Patent #:
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Issue Dt:
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02/19/2013
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Application #:
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13046789
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Filing Dt:
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03/14/2011
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Publication #:
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Pub Dt:
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09/20/2012
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Title:
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ADAPTIVE BANDWIDTH PHASE-LOCKED LOOP
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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13046815
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Filing Dt:
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03/14/2011
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Publication #:
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Pub Dt:
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09/20/2012
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Title:
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METHOD OF RE-ORDERING RECEIVED DATA BLOCKS IN HYBRID AUTOMATIC REPEAT REQUEST TELECOMMUNICATION SYSTEM
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Patent #:
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Issue Dt:
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07/16/2013
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Application #:
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13047800
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Filing Dt:
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03/15/2011
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Publication #:
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Pub Dt:
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10/06/2011
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Title:
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METHOD FOR DETECTING AUDIO SIGNAL TRANSIENT AND TIME-SCALE MODIFICATION BASED ON SAME
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Patent #:
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Issue Dt:
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01/15/2013
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Application #:
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13050932
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Filing Dt:
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03/18/2011
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Publication #:
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Pub Dt:
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09/20/2012
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Title:
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SYNCHRONOUS DATA PROCESSING SYSTEM FOR RELIABLE TRANSFER OF DATA IRRESPECTIVE OF PROPAGATION DELAYS AND PROCESS, VOLTAGE AND TEMPERATURE (PVT) VARIATIONS
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Patent #:
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Issue Dt:
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11/27/2012
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Application #:
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13050948
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Filing Dt:
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03/18/2011
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Publication #:
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Pub Dt:
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09/20/2012
| | | | |
Title:
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MEMORY CONTROLLER ADDRESS AND DATA PIN MULTIPLEXING
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Patent #:
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Issue Dt:
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08/11/2015
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Application #:
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13051611
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Filing Dt:
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03/18/2011
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Publication #:
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Pub Dt:
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09/20/2012
| | | | |
Title:
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VOLTAGE-CONTROLLED OSCILLATORS AND RELATED SYSTEMS
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Patent #:
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Issue Dt:
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10/22/2013
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Application #:
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13053962
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Filing Dt:
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03/22/2011
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Publication #:
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Pub Dt:
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09/27/2012
| | | | |
Title:
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SELECTIVE CHECKBIT MODIFICATION FOR ERROR CORRECTION
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Patent #:
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|
Issue Dt:
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12/17/2013
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Application #:
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13059084
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Filing Dt:
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02/15/2011
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Publication #:
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Pub Dt:
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06/09/2011
| | | | |
Title:
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SYSTEM AND METHOD FOR COMMUNICATING ON AN ELECTRICAL BUS
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Patent #:
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Issue Dt:
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01/20/2015
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Application #:
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13068335
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Filing Dt:
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05/09/2011
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Publication #:
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Pub Dt:
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11/17/2011
| | | | |
Title:
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ELECTROSTATIC OCCUPANT DETECTION SYSTEM
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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13071025
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Filing Dt:
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03/24/2011
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Publication #:
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Pub Dt:
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09/27/2012
| | | | |
Title:
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SELECTABLE THRESHOLD RESET CIRCUIT
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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13075768
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Filing Dt:
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03/30/2011
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Publication #:
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Pub Dt:
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10/04/2012
| | | | |
Title:
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CIRCUIT FOR PREVENTING A DUMMY READ IN A MEMORY
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Patent #:
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Issue Dt:
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04/22/2014
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Application #:
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13077963
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Filing Dt:
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03/31/2011
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Publication #:
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Pub Dt:
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10/04/2012
| | | | |
Title:
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METHOD AND SYSTEM TO COMPENSATE FOR TEMPERATURE AND PRESSURE IN PIEZO RESISTIVE DEVICES
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Patent #:
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Issue Dt:
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08/05/2014
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Application #:
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13080944
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Filing Dt:
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04/06/2011
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Publication #:
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Pub Dt:
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04/19/2012
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Title:
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MEMORY CONTROLLER AND METHOD FOR ACCESSING A PLURALITY OF NON-VOLATILE MEMORY ARRAYS
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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13088579
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Filing Dt:
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04/18/2011
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Publication #:
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Pub Dt:
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10/18/2012
| | | | |
Title:
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MEMS DEVICE WITH CENTRAL ANCHOR FOR STRESS ISOLATION
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Patent #:
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Issue Dt:
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12/08/2015
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Application #:
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13090056
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Filing Dt:
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04/19/2011
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Publication #:
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Pub Dt:
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10/25/2012
| | | | |
Title:
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DYNAMIC LOCKSTEP CACHE MEMORY REPLACEMENT LOGIC
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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13090057
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Filing Dt:
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04/19/2011
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Publication #:
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Pub Dt:
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10/25/2012
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Title:
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CACHE MEMORY WITH DYNAMIC LOCKSTEP SUPPORT
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Patent #:
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Issue Dt:
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08/27/2013
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Application #:
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13093865
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Filing Dt:
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04/26/2011
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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SYSTEM FOR PERFORMING ELECTRICAL CHARACTERIZATION OF ASYNCHRONOUS INTEGRATED CIRCUIT INTERFACES
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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13094110
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Filing Dt:
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04/26/2011
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Publication #:
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Pub Dt:
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11/01/2012
| | | | |
Title:
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A REGISTER RENAMING SCHEME WITH CHECKPOINT REPAIR IN A PROCESSING DEVICE
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Patent #:
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Issue Dt:
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06/23/2015
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Application #:
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13096282
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Filing Dt:
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04/28/2011
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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MICROPROCESSOR SYSTEMS AND METHODS FOR A COMBINED REGISTER FILE AND CHECKPOINT REPAIR REGISTER
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13096320
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Filing Dt:
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04/28/2011
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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LOAD CONTROL AND PROTECTION SYSTEM
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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13097411
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Filing Dt:
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04/29/2011
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Publication #:
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Pub Dt:
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11/01/2012
| | | | |
Title:
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VOLTAGE REGULATOR WITH DIFFERENT INVERTING GAIN STAGES
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Patent #:
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Issue Dt:
|
12/10/2013
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Application #:
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13097721
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Filing Dt:
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04/29/2011
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Publication #:
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|
Pub Dt:
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11/01/2012
| | | | |
Title:
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SELECTIVE ERROR DETECTION AND ERROR CORRECTION FOR A MEMORY INTERFACE
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Patent #:
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Issue Dt:
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12/03/2013
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Application #:
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13101793
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Filing Dt:
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05/05/2011
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Publication #:
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Pub Dt:
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11/08/2012
| | | | |
Title:
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MEMS DEVICE WITH IMPACTING STRUCTURE FOR ENHANCED RESISTANCE TO STICTION
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Patent #:
|
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Issue Dt:
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06/17/2014
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Application #:
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13103609
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Filing Dt:
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05/09/2011
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Publication #:
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Pub Dt:
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11/15/2012
| | | | |
Title:
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SELECTIVE ROUTING OF LOCAL MEMORY ACCESSES AND DEVICE THEREOF
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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13104449
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Filing Dt:
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05/10/2011
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Publication #:
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Pub Dt:
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11/15/2012
| | | | |
Title:
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PHASE LOCKED LOOP CIRCUIT HAVING A VOLTAGE CONTROLLED OSCILLATOR WITH IMPROVED BANDWIDTH
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Patent #:
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Issue Dt:
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02/17/2015
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Application #:
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13106703
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Filing Dt:
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05/12/2011
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Publication #:
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Pub Dt:
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11/15/2012
| | | | |
Title:
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SYSTEM AND METHOD FOR SCALABLE MOVEMENT AND REPLICATION OF DATA
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Patent #:
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Issue Dt:
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12/02/2014
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Application #:
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13116325
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Filing Dt:
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05/26/2011
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Publication #:
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Pub Dt:
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11/29/2012
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Title:
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MICROPROCESSOR SYSTEMS AND METHODS FOR HANDLING INSTRUCTIONS WITH MULTIPLE DEPENDENCIES
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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13119205
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Filing Dt:
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03/16/2011
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Publication #:
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Pub Dt:
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07/07/2011
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Title:
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FLEXIBLE BUS DRIVER
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Patent #:
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Issue Dt:
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08/28/2012
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Application #:
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13120707
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Filing Dt:
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03/24/2011
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Publication #:
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Pub Dt:
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07/21/2011
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Title:
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WIRELESS COMMUNICATION DEVICE AND SEMICONDUCTOR PACKAGE DEVICE HAVING A POWER AMPLIFIER THEREFOR
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Patent #:
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Issue Dt:
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03/19/2013
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Application #:
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13122321
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Filing Dt:
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04/01/2011
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Publication #:
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Pub Dt:
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08/04/2011
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Title:
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COMPLEMENTARY BAND-GAP VOLTAGE REFERENCE CIRCUIT
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Patent #:
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Issue Dt:
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12/31/2013
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Application #:
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13125856
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Filing Dt:
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04/25/2011
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Publication #:
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Pub Dt:
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09/01/2011
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Title:
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MULTIMODE VOLTAGE REGULATOR AND METHOD FOR PROVIDING A MULTIMODE VOLTAGE REGULATOR OUTPUT VOLTAGE AND AN OUTPUT CURRENT TO A LOAD
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
|
13126038
|
Filing Dt:
|
04/26/2011
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
METHOD AND APPARATUS FOR GENERATING A CLOCK SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13129936
|
Filing Dt:
|
05/18/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
HIGH POWER SEMICONDUCTOR DEVICE FOR WIRELESS APPLICATIONS AND METHOD OF FORMING A HIGH POWER SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
13142281
|
Filing Dt:
|
06/27/2011
|
Publication #:
|
|
Pub Dt:
|
04/12/2012
| | | | |
Title:
|
INTEGRATED CIRCUIT COMPRISING DEFLICKER UNIT FOR FILTERING IMAGE DATA, AND A METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13143550
|
Filing Dt:
|
07/07/2011
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
PROCESSING DATA FLOWS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
13143551
|
Filing Dt:
|
07/07/2011
|
Publication #:
|
|
Pub Dt:
|
02/02/2012
| | | | |
Title:
|
PRIORITY SEARCH TREES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13145122
|
Filing Dt:
|
07/19/2011
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
INTEGRATED CIRCUIT COMPRISING FREQUENCY GENERATION CIRCUITRY FOR CONTROLLING A FREQUENCY SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13145125
|
Filing Dt:
|
07/19/2011
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
INTEGRATED CIRCUIT COMPRISING FREQUENCY GENERATION CIRCUITRY FOR CONTROLLING A FREQUENCY SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13149217
|
Filing Dt:
|
05/31/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
CONTROL OF INTERRUPT GENERATION FOR CACHE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13149304
|
Filing Dt:
|
05/31/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
CACHE LOCKING CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13150322
|
Filing Dt:
|
06/01/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
DOUBLE EDGE TRIGGERED FLIP FLOP
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13156346
|
Filing Dt:
|
06/09/2011
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
Title:
|
METHOD AND SYSTEM FOR ADDRESS CONFLICT RESOLUTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13157549
|
Filing Dt:
|
06/10/2011
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
Title:
|
WRITING DATA TO SYSTEM MEMORY IN A DATA PROCESSING SYSTEM IN WHICH CACHE LINE STATES ARE TRACKED
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13159878
|
Filing Dt:
|
06/14/2011
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
Title:
|
SELECTIVE MASKING FOR ERROR CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13162835
|
Filing Dt:
|
06/17/2011
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
Title:
|
BRANCH TARGET BUFFER ADDRESSING IN A DATA PROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13164009
|
Filing Dt:
|
06/20/2011
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR SNOOP-AND-LEARN INTELLIGENCE IN DATA PLANE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13168331
|
Filing Dt:
|
06/24/2011
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
BANDWIDTH CONTROL FOR A DIRECT MEMORY ACCESS UNIT WITHIN A DATA PROCESSING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13169397
|
Filing Dt:
|
06/27/2011
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
WORD LINE FAULT DETECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13169664
|
Filing Dt:
|
06/27/2011
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
USING BUILT-IN SELF TEST FOR PREVENTING SIDE CHANNEL SECURITY ATTACKS ON MULTI-PROCESSOR SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13170210
|
Filing Dt:
|
06/28/2011
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
SYSTEM ON A CHIP WITH INTERLEAVED SETS OF PADS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
13171989
|
Filing Dt:
|
06/29/2011
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
METHOD FOR FORMING A TOROIDAL INDUCTOR IN A SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
13179295
|
Filing Dt:
|
07/08/2011
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
ELECTRONIC ELEMENTS AND DEVICES WITH TRENCH UNDER BOND PAD FEATURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13182734
|
Filing Dt:
|
07/14/2011
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
Title:
|
SYSTEMS AND METHODS FOR MEMORY REGION DESCRIPTOR ATTRIBUTE OVERRIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
13186091
|
Filing Dt:
|
07/19/2011
|
Publication #:
|
|
Pub Dt:
|
01/24/2013
| | | | |
Title:
|
SYSTEMS AND METHODS FOR DATA CONVERSION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13186106
|
Filing Dt:
|
07/19/2011
|
Publication #:
|
|
Pub Dt:
|
01/24/2013
| | | | |
Title:
|
SYSTEMS AND METHODS FOR DATA CONVERSION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
13188084
|
Filing Dt:
|
07/21/2011
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
THROUGH SUBSTRATE VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13191456
|
Filing Dt:
|
07/27/2011
|
Publication #:
|
|
Pub Dt:
|
01/31/2013
| | | | |
Title:
|
METHOD FOR PARTITIONING SCAN CHAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13191459
|
Filing Dt:
|
07/27/2011
|
Publication #:
|
|
Pub Dt:
|
01/31/2013
| | | | |
Title:
|
POWER SUPPLY AND DATA SIGNAL INTERFACE CIRCUIT WITH OVERVOLTAGE PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
13194714
|
Filing Dt:
|
07/29/2011
|
Publication #:
|
|
Pub Dt:
|
01/31/2013
| | | | |
Title:
|
OSCILLATOR SYSTEMS HAVING ANNULAR RESONANT CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13210281
|
Filing Dt:
|
08/15/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
METHOD AND DEVICE FOR CONTROLLING DEBUG EVENT RESOURCES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13210563
|
Filing Dt:
|
08/16/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
ATTACHING A MEMS TO A BONDING WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
13210566
|
Filing Dt:
|
08/16/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
SYSTEMS AND METHODS FOR HANDLING INSTRUCTIONS OF IN-ORDER AND OUT-OF-ORDER EXECUTION QUEUES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13212420
|
Filing Dt:
|
08/18/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
SYSTEMS AND METHODS FOR HANDLING INSTRUCTIONS OF IN-ORDER AND OUT-OF-ORDER EXECUTION QUEUES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2016
|
Application #:
|
13213387
|
Filing Dt:
|
08/19/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
DATA PROCESSING SYSTEM OPERABLE IN SINGLE AND MULTI-THREAD MODES AND HAVING MULTIPLE CACHES AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2015
|
Application #:
|
13213900
|
Filing Dt:
|
08/19/2011
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
Title:
|
MEMORY MANAGEMENT UNIT TAG MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13222323
|
Filing Dt:
|
08/31/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
MOFSET MISMATCH CHARACTERIZATION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
13222335
|
Filing Dt:
|
08/31/2011
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
MOFSET MISMATCH CHARACTERIZATION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13234305
|
Filing Dt:
|
09/16/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
MEMORY MANAGEMENT UNIT (MMU) HAVING REGION DESCRIPTOR GLOBALIZATION CONTROLS AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13235499
|
Filing Dt:
|
09/19/2011
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
LEVEL SHIFTER CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2014
|
Application #:
|
13239649
|
Filing Dt:
|
09/22/2011
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
MULTI-PROCESSOR DATA PROCESSING SYSTEM HAVING SYNCHRONIZED EXIT FROM DEBUG MODE AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13249256
|
Filing Dt:
|
09/30/2011
|
Publication #:
|
|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
METHOD AND APPARATUS FOR CALCULATING SENSOR MODELLING COEFFICIENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13249271
|
Filing Dt:
|
09/30/2011
|
Publication #:
|
|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
METHOD AND CIRCUIT FOR CALCULATING SENSOR MODELLING COEFFICIENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13249829
|
Filing Dt:
|
09/30/2011
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
MEMORY PROTECTION UNIT (MPU) HAVING A SHARED PORTION AND METHOD OF OPERATION
|
|