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Reel/Frame:034979/0850   Pages: 15
Recorded: 02/12/2015
Attorney Dkt #:HLNAND PORTFOLIO
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 78
1
Patent #:
Issue Dt:
06/22/2010
Application #:
11495609
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
01/31/2008
Title:
PULSE COUNTER WITH CLOCK EDGE RECOVERY
2
Patent #:
Issue Dt:
04/15/2014
Application #:
11529293
Filing Dt:
09/29/2006
Publication #:
Pub Dt:
04/03/2008
Title:
PACKET BASED ID GENERATION FOR SERIALLY INTERCONNECTED DEVICES
3
Patent #:
Issue Dt:
03/24/2009
Application #:
11565327
Filing Dt:
11/30/2006
Publication #:
Pub Dt:
06/05/2008
Title:
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
4
Patent #:
Issue Dt:
10/19/2010
Application #:
11567551
Filing Dt:
12/06/2006
Publication #:
Pub Dt:
06/12/2008
Title:
APPARATUS AND METHOD FOR CAPTURING SERIAL INPUT DATA
5
Patent #:
Issue Dt:
03/17/2015
Application #:
11613563
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
ID GENERATION APPARATUS AND METHOD FOR SERIALLY INTERCONNECTED DEVICES
6
Patent #:
Issue Dt:
08/30/2011
Application #:
11692326
Filing Dt:
03/28/2007
Publication #:
Pub Dt:
09/04/2008
Title:
APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPE OF SERIALLY INTERCONNECTED DEVICES
7
Patent #:
Issue Dt:
12/14/2010
Application #:
11692446
Filing Dt:
03/28/2007
Publication #:
Pub Dt:
08/14/2008
Title:
APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION
8
Patent #:
Issue Dt:
12/11/2012
Application #:
11692452
Filing Dt:
03/28/2007
Publication #:
Pub Dt:
02/10/2011
Title:
APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE
9
Patent #:
Issue Dt:
02/21/2012
Application #:
11843024
Filing Dt:
08/22/2007
Publication #:
Pub Dt:
08/21/2008
Title:
REDUCED PIN COUNT INTERFACE
10
Patent #:
Issue Dt:
02/15/2011
Application #:
11873475
Filing Dt:
10/17/2007
Publication #:
Pub Dt:
04/23/2009
Title:
SINGLE-STROBE OPERATION OF MEMORY DEVICES
11
Patent #:
NONE
Issue Dt:
Application #:
11897105
Filing Dt:
08/29/2007
Publication #:
Pub Dt:
03/05/2009
Title:
Daisy-chain memory configuration and usage
12
Patent #:
Issue Dt:
11/16/2010
Application #:
11941131
Filing Dt:
11/16/2007
Publication #:
Pub Dt:
05/21/2009
Title:
METHODS AND SYSTEMS FOR FAILURE ISOLATION AND DATA RECOVERY IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES
13
Patent #:
Issue Dt:
01/04/2011
Application #:
11959996
Filing Dt:
12/19/2007
Publication #:
Pub Dt:
09/18/2008
Title:
METHODS AND APPARATUS FOR CLOCK SIGNAL SYNCHRONIZATION IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES
14
Patent #:
Issue Dt:
11/26/2013
Application #:
12013148
Filing Dt:
01/11/2008
Publication #:
Pub Dt:
07/16/2009
Title:
RING-OF-CLUSTERS NETWORK TOPOLOGIES
15
Patent #:
Issue Dt:
08/02/2011
Application #:
12025177
Filing Dt:
02/04/2008
Publication #:
Pub Dt:
08/14/2008
Title:
APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPES OF SERIES-CONNECTED DEVICES OF MIXED TYPE
16
Patent #:
Issue Dt:
03/22/2011
Application #:
12028335
Filing Dt:
02/08/2008
Publication #:
Pub Dt:
10/22/2009
Title:
DATA CHANNEL TEST APPARATUS AND METHOD THEREOF
17
Patent #:
Issue Dt:
09/14/2010
Application #:
12034686
Filing Dt:
02/21/2008
Publication #:
Pub Dt:
08/28/2008
Title:
DATA FLOW CONTROL IN MULTIPLE INDEPENDENT PORT
18
Patent #:
Issue Dt:
09/02/2014
Application #:
12141384
Filing Dt:
06/18/2008
Publication #:
Pub Dt:
06/18/2009
Title:
SEMICONDUCTOR MEMORY DEVICE SUITABLE FOR INTERCONNECTION IN A RING TOPOLOGY
19
Patent #:
Issue Dt:
07/15/2014
Application #:
12168091
Filing Dt:
07/04/2008
Publication #:
Pub Dt:
06/18/2009
Title:
CLOCK REPRODUCING AND TIMING METHOD IN A SYSTEM HAVING A PLURALITY OF DEVICES
20
Patent #:
Issue Dt:
03/20/2012
Application #:
12169115
Filing Dt:
07/08/2008
Publication #:
Pub Dt:
01/14/2010
Title:
MIXED DATA RATES IN MEMORY DEVICES AND SYSTEMS
21
Patent #:
Issue Dt:
03/19/2019
Application #:
12212902
Filing Dt:
09/18/2008
Publication #:
Pub Dt:
03/18/2010
Title:
MASS DATA STORAGE SYSTEM WITH NON-VOLATILE MEMORY MODULES
22
Patent #:
Issue Dt:
05/15/2012
Application #:
12241832
Filing Dt:
09/30/2008
Publication #:
Pub Dt:
04/01/2010
Title:
SERIAL-CONNECTED MEMORY SYSTEM WITH OUTPUT DELAY ADJUSTMENT
23
Patent #:
Issue Dt:
04/17/2012
Application #:
12241960
Filing Dt:
09/30/2008
Publication #:
Pub Dt:
04/01/2010
Title:
SERIAL-CONNECTED MEMORY SYSTEM WITH DUTY CYCLE CORRECTION
24
Patent #:
Issue Dt:
03/06/2012
Application #:
12254315
Filing Dt:
10/20/2008
Publication #:
Pub Dt:
08/06/2009
Title:
SELECTIVE BROADCASTING OF DATA IN SERIES CONNECTED DEVICES
25
Patent #:
Issue Dt:
06/18/2013
Application #:
12325074
Filing Dt:
11/28/2008
Publication #:
Pub Dt:
06/18/2009
Title:
MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT TO CLOCK
26
Patent #:
Issue Dt:
10/11/2011
Application #:
12337841
Filing Dt:
12/18/2008
Publication #:
Pub Dt:
06/24/2010
Title:
DEVICE AND METHOD FOR TRANSFERRING DATA TO A NON-VOLATILE MEMORY DEVICE
27
Patent #:
Issue Dt:
06/25/2013
Application #:
12367056
Filing Dt:
02/06/2009
Publication #:
Pub Dt:
05/13/2010
Title:
SYSTEM INCLUDING A PLURALITY OF ENCAPSULATED SEMICONDUCTOR CHIPS
28
Patent #:
Issue Dt:
03/16/2010
Application #:
12391810
Filing Dt:
02/24/2009
Publication #:
Pub Dt:
06/25/2009
Title:
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
29
Patent #:
Issue Dt:
06/12/2012
Application #:
12399315
Filing Dt:
03/06/2009
Publication #:
Pub Dt:
05/06/2010
Title:
DATA MIRRORING IN SERIAL-CONNECTED MEMORY SYSTEM
30
Patent #:
Issue Dt:
11/04/2014
Application #:
12418892
Filing Dt:
04/06/2009
Publication #:
Pub Dt:
06/24/2010
Title:
ERROR DETECTION METHOD AND A SYSTEM INCLUDING ONE OR MORE MEMORY DEVICES
31
Patent #:
Issue Dt:
08/27/2013
Application #:
12504156
Filing Dt:
07/16/2009
Publication #:
Pub Dt:
01/20/2011
Title:
SIMULTANEOUS READ AND WRITE DATA TRANSFER
32
Patent #:
Issue Dt:
11/29/2011
Application #:
12564492
Filing Dt:
09/22/2009
Publication #:
Pub Dt:
02/10/2011
Title:
SEMICONDUCTOR MEMORY WITH MULTIPLE WORDLINE SELECTION
33
Patent #:
Issue Dt:
06/05/2012
Application #:
12640388
Filing Dt:
12/17/2009
Publication #:
Pub Dt:
06/24/2010
Title:
SEMICONDUCTOR DEVICE WITH MAIN MEMORY UNIT AND AUXILIARY MEMORY UNIT REQUIRING PRESET OPERATION
34
Patent #:
Issue Dt:
03/22/2011
Application #:
12698585
Filing Dt:
02/02/2010
Publication #:
Pub Dt:
06/03/2010
Title:
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
35
Patent #:
Issue Dt:
08/06/2013
Application #:
12770376
Filing Dt:
04/29/2010
Publication #:
Pub Dt:
11/25/2010
Title:
CONFIGURABLE MODULE AND MEMORY SUBSYSTEM
36
Patent #:
Issue Dt:
11/12/2013
Application #:
12782911
Filing Dt:
05/19/2010
Publication #:
Pub Dt:
09/29/2011
Title:
MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES
37
Patent #:
Issue Dt:
04/17/2012
Application #:
12851884
Filing Dt:
08/06/2010
Publication #:
Pub Dt:
12/02/2010
Title:
DATA FLOW CONTROL IN MULTIPLE INDEPENDENT PORT
38
Patent #:
Issue Dt:
12/02/2014
Application #:
12879543
Filing Dt:
09/10/2010
Publication #:
Pub Dt:
12/30/2010
Title:
APPARATUS AND METHOD FOR CAPTURING SERIAL INPUT DATA
39
Patent #:
Issue Dt:
06/05/2012
Application #:
12892215
Filing Dt:
09/28/2010
Publication #:
Pub Dt:
01/20/2011
Title:
APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION
40
Patent #:
Issue Dt:
05/14/2013
Application #:
12945280
Filing Dt:
11/12/2010
Publication #:
Pub Dt:
03/10/2011
Title:
METHODS AND SYSTEMS FOR FAILURE ISOLATION AND DATA RECOVERY IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES
41
Patent #:
Issue Dt:
04/29/2014
Application #:
12948186
Filing Dt:
11/17/2010
Publication #:
Pub Dt:
03/10/2011
Title:
METHODS AND APPARATUS FOR CLOCK SIGNAL SYNCHRONIZATION IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES
42
Patent #:
Issue Dt:
03/26/2013
Application #:
12984987
Filing Dt:
01/05/2011
Publication #:
Pub Dt:
04/28/2011
Title:
SINGLE-STROBE OPERATION OF MEMORY DEVICES
43
Patent #:
Issue Dt:
06/11/2013
Application #:
13012754
Filing Dt:
01/24/2011
Publication #:
Pub Dt:
12/01/2011
Title:
HIGH-SPEED INTERFACE FOR DAISY-CHAINED DEVICES
44
Patent #:
NONE
Issue Dt:
Application #:
13023838
Filing Dt:
02/09/2011
Publication #:
Pub Dt:
10/20/2011
Title:
STATUS INDICATION IN A SYSTEM HAVING A PLURALITY OF MEMORY DEVICES
45
Patent #:
Issue Dt:
12/20/2011
Application #:
13030785
Filing Dt:
02/18/2011
Publication #:
Pub Dt:
06/16/2011
Title:
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
46
Patent #:
Issue Dt:
03/05/2013
Application #:
13033294
Filing Dt:
02/23/2011
Publication #:
Pub Dt:
06/23/2011
Title:
DATA CHANNEL TEST APPARATUS AND METHOD THEREOF
47
Patent #:
Issue Dt:
09/23/2014
Application #:
13048154
Filing Dt:
03/15/2011
Publication #:
Pub Dt:
10/27/2011
Title:
SYSTEM OF INTERCONNECTED NONVOLATILE MEMORIES HAVING AUTOMATIC STATUS PACKET
48
Patent #:
NONE
Issue Dt:
Application #:
13102310
Filing Dt:
05/06/2011
Publication #:
Pub Dt:
11/10/2011
Title:
METHOD AND APPARATUS FOR CONCURRENTLY READING A PLURALITY OF MEMORY DEVICES USING A SINGLE BUFFER
49
Patent #:
Issue Dt:
07/24/2012
Application #:
13168157
Filing Dt:
06/24/2011
Publication #:
Pub Dt:
10/20/2011
Title:
APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPES OF SERIES-CONNECTED DEVICES OF MIXED TYPE
50
Patent #:
Issue Dt:
09/02/2014
Application #:
13364685
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
05/31/2012
Title:
REDUCED PIN COUNT INTERFACE
51
Patent #:
Issue Dt:
09/02/2014
Application #:
13401087
Filing Dt:
02/21/2012
Publication #:
Pub Dt:
06/13/2013
Title:
INDEPENDENT WRITE AND READ CONTROL IN SERIALLY-CONNECTED DEVICES
52
Patent #:
Issue Dt:
07/23/2013
Application #:
13418478
Filing Dt:
03/13/2012
Publication #:
Pub Dt:
07/05/2012
Title:
DATA FLOW CONTROL IN MULTIPLE INDEPENDENT PORT
53
Patent #:
NONE
Issue Dt:
Application #:
13425801
Filing Dt:
03/21/2012
Publication #:
Pub Dt:
05/23/2013
Title:
POWER SAVING METHODS FOR USE IN A SYSTEM OF SERIALLY CONNECTED SEMICONDUCTOR DEVICES
54
Patent #:
NONE
Issue Dt:
Application #:
13588195
Filing Dt:
08/17/2012
Publication #:
Pub Dt:
04/18/2013
Title:
CONNECTION OF MULTIPLE SEMICONDUCTOR MEMORY DEVICES WITH CHIP ENABLE FUNCTION
55
Patent #:
Issue Dt:
04/14/2015
Application #:
13643317
Filing Dt:
11/06/2012
Publication #:
Pub Dt:
04/04/2013
Title:
SERIALLY CONNECTED MEMORY HAVING SUBDIVIDED DATA INTERFACE
56
Patent #:
Issue Dt:
10/13/2015
Application #:
13665181
Filing Dt:
10/31/2012
Publication #:
Pub Dt:
05/02/2013
Title:
FLASH MEMORY MODULE AND MEMORY SUBSYSTEM
57
Patent #:
Issue Dt:
04/08/2014
Application #:
13671248
Filing Dt:
11/07/2012
Publication #:
Pub Dt:
03/14/2013
Title:
APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE
58
Patent #:
NONE
Issue Dt:
Application #:
13675163
Filing Dt:
11/13/2012
Publication #:
Pub Dt:
05/16/2013
Title:
PACKAGE HAVING STACKED MEMORY DIES WITH SERIALLY CONNECTED BUFFER DIES
59
Patent #:
Issue Dt:
09/08/2015
Application #:
13720951
Filing Dt:
12/19/2012
Publication #:
Pub Dt:
06/27/2013
Title:
SOLID STATE DRIVE MEMORY SYSTEM
60
Patent #:
Issue Dt:
10/13/2015
Application #:
13750046
Filing Dt:
01/25/2013
Publication #:
Pub Dt:
08/01/2013
Title:
METHOD AND APPARATUS FOR CONNECTING MEMORY DIES TO FORM A MEMORY SYSTEM
61
Patent #:
Issue Dt:
06/03/2014
Application #:
13774477
Filing Dt:
02/22/2013
Title:
OPERATIONAL MODE CONTROL IN SERIAL-CONNECTED MEMORY BASED ON IDENTIFIER
62
Patent #:
Issue Dt:
10/18/2016
Application #:
13835968
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
03/20/2014
Title:
FLASH MEMORY CONTROLLER HAVING DUAL MODE PIN-OUT
63
Patent #:
NONE
Issue Dt:
Application #:
13836113
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
05/01/2014
Title:
FLASH MEMORY CONTROLLER HAVING MULTI MODE PIN-OUT
64
Patent #:
Issue Dt:
03/18/2014
Application #:
13836702
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
08/08/2013
Title:
SINGLE-STROBE OPERATION OF MEMORY DEVICES
65
Patent #:
Issue Dt:
09/16/2014
Application #:
13887937
Filing Dt:
05/06/2013
Publication #:
Pub Dt:
09/19/2013
Title:
MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT TO CLOCK
66
Patent #:
NONE
Issue Dt:
Application #:
13903418
Filing Dt:
05/28/2013
Publication #:
Pub Dt:
12/05/2013
Title:
RING TOPOLOGY STATUS INDICATION
67
Patent #:
NONE
Issue Dt:
Application #:
13914126
Filing Dt:
06/10/2013
Publication #:
Pub Dt:
10/17/2013
Title:
HIGH SPEED INTERFACE FOR DAISY-CHAINED DEVICES
68
Patent #:
Issue Dt:
12/09/2014
Application #:
13917728
Filing Dt:
06/14/2013
Publication #:
Pub Dt:
10/17/2013
Title:
SYSTEM INCLUDING A PLURALITY OF ENCAPSULATED SEMICONDUCTOR CHIPS
69
Patent #:
Issue Dt:
07/01/2014
Application #:
13957713
Filing Dt:
08/02/2013
Publication #:
Pub Dt:
12/05/2013
Title:
CONFIGURABLE MODULE AND MEMORY SUBSYSTEM
70
Patent #:
Issue Dt:
11/25/2014
Application #:
13962062
Filing Dt:
08/08/2013
Publication #:
Pub Dt:
01/09/2014
Title:
SIMULTANEOUS READ AND WRITE DATA TRANSFER
71
Patent #:
Issue Dt:
11/25/2014
Application #:
14045857
Filing Dt:
10/04/2013
Publication #:
Pub Dt:
01/30/2014
Title:
MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES
72
Patent #:
Issue Dt:
12/02/2014
Application #:
14057102
Filing Dt:
10/18/2013
Publication #:
Pub Dt:
04/24/2014
Title:
RING-OF-CLUSTERS NETWORK TOPOLOGIES
73
Patent #:
Issue Dt:
06/09/2015
Application #:
14066748
Filing Dt:
10/30/2013
Publication #:
Pub Dt:
05/15/2014
Title:
PLL LOCKING CONTROL IN DAISY CHAINED MEMORY SYSTEM
74
Patent #:
NONE
Issue Dt:
Application #:
14185401
Filing Dt:
02/20/2014
Publication #:
Pub Dt:
06/19/2014
Title:
PACKET DATA ID GENERATION FOR SERIALLY INTERCONNECTED DEVICES
75
Patent #:
Issue Dt:
09/29/2015
Application #:
14294372
Filing Dt:
06/03/2014
Publication #:
Pub Dt:
11/20/2014
Title:
CLOCK REPRODUCING AND TIMING METHOD IN A SYSTEM HAVING A PLURALITY OF DEVICES
76
Patent #:
Issue Dt:
10/25/2016
Application #:
14478824
Filing Dt:
09/05/2014
Publication #:
Pub Dt:
04/02/2015
Title:
Method and Apparatus for Testing Surface Mounted Devices
77
Patent #:
NONE
Issue Dt:
Application #:
14486484
Filing Dt:
09/15/2014
Publication #:
Pub Dt:
03/19/2015
Title:
MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT TO CLOCK
78
Patent #:
NONE
Issue Dt:
Application #:
14503714
Filing Dt:
10/01/2014
Publication #:
Pub Dt:
01/15/2015
Title:
ERROR DETECTION METHOD AND A SYSTEM INCLUDING ONE OR MORE MEMORY DEVICE
Assignors
1
Exec Dt:
02/10/2015
2
Exec Dt:
02/10/2015
Assignee
1
390 MARCH ROAD
SUITE 100
OTTAWA, CANADA K2K 0G7
Correspondence name and address
CONVERSANT IP MANAGEMENT CORP
5601 GRANITE PARKWAY
SUITE 1300
PLANO, TX 75024

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