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Patent #:
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Issue Dt:
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01/26/2010
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Application #:
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10537857
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Filing Dt:
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06/07/2005
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Publication #:
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Pub Dt:
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03/16/2006
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Title:
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METHOD, CIRCUIT AND SYSTEM FOR ERASING ONE OR MORE NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10635974
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Filing Dt:
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08/07/2003
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Title:
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MEMORY CIRCUIT FOR PROVIDING WORD LINE REDUNDANCY IN A MEMORY SECTOR
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10653388
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Filing Dt:
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09/03/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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MEMORY ARRAY PROGRAMMING CIRCUIT AND A METHOD FOR USING THE CIRCUIT
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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10656251
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Filing Dt:
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09/08/2003
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Publication #:
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Pub Dt:
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03/11/2004
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Title:
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METHOD FOR ERASING A MEMORY CELL
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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10662535
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Filing Dt:
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09/16/2003
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Publication #:
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Pub Dt:
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03/17/2005
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Title:
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READING ARRAY CELL WITH MATCHED REFERENCE CELL
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Patent #:
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Issue Dt:
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07/26/2005
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Application #:
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10689054
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Filing Dt:
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10/21/2003
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Publication #:
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Pub Dt:
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04/21/2005
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Title:
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CLASS AB VOLTAGE REGULATOR
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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10695448
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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07/15/2004
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Title:
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METHOD CIRCUIT AND SYSTEM FOR DETERMINING A REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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11/14/2006
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Application #:
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10695449
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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METHOD, SYSTEM AND CIRCUIT FOR PROGRAMMING A NON-VOLATILE MEMORY ARRAY
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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10695457
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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07/15/2004
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Title:
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METHOD CIRCUIT AND SYSTEM FOR READ ERROR DETECTION IN A NON-VOLATILE MEMORY ARRAY
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10715366
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Filing Dt:
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11/19/2003
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Publication #:
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Pub Dt:
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07/15/2004
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Title:
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MEMORY CONTROL CIRCUIT, MEMORY DEVICE, AND MICROCOMPUTER
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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10738301
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Filing Dt:
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12/16/2003
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Title:
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METHOD AND DEVICE FOR PROGRAMMING CELLS IN A MEMORY ARRAY IN A NARROW DISTRIBUTION
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10740616
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Filing Dt:
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12/22/2003
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Publication #:
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Pub Dt:
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07/08/2004
| | | | |
Title:
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CHARGE PUMP STAGE WITH BODY EFFECT MINIMIZATION
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10747217
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Filing Dt:
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12/30/2003
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Publication #:
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Pub Dt:
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03/17/2005
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Title:
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METHOD FOR OPERATING A MEMORY DEVICE
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10754948
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Filing Dt:
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01/08/2004
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Title:
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INTEGRATED ONO PROCESSING FOR SEMICONDUCTOR DEVICES USING IN-SITU STEAM GENERATION (ISSG) PROCESS
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10774806
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Filing Dt:
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02/10/2004
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Publication #:
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Pub Dt:
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08/11/2005
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Title:
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HIGH VOLTAGE LOW POWER DRIVER
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Patent #:
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Issue Dt:
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11/28/2006
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Application #:
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10810683
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Filing Dt:
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03/29/2004
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Publication #:
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Pub Dt:
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11/04/2004
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Title:
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APPARATUS AND METHODS FOR MULTI-LEVEL SENSING IN A MEMORY ARRAY
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Patent #:
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Issue Dt:
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07/13/2010
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Application #:
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10826375
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Filing Dt:
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04/19/2004
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Publication #:
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Pub Dt:
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10/20/2005
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Title:
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METHOD FOR READING A MEMORY ARRAY WITH NEIGHBOR EFFECT CANCELLATION
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Patent #:
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Issue Dt:
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11/25/2014
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Application #:
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10861581
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Filing Dt:
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06/04/2004
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Title:
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Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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10862401
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Filing Dt:
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06/08/2004
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Publication #:
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Pub Dt:
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12/08/2005
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Title:
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POWER-UP AND BGREF CIRCUITRY
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Patent #:
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Issue Dt:
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03/06/2007
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Application #:
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10862404
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Filing Dt:
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06/08/2004
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Publication #:
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Pub Dt:
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02/23/2006
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Title:
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REPLENISHMENT FOR INTERNAL VOLTAGE
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Patent #:
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Issue Dt:
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08/14/2007
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Application #:
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10862405
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Filing Dt:
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06/08/2004
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Publication #:
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Pub Dt:
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12/08/2005
| | | | |
Title:
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MOS CAPACITOR WITH REDUCED PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10863529
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Filing Dt:
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06/09/2004
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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TWO BIT NON-VOLATILE ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING
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Patent #:
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Issue Dt:
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04/29/2008
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Application #:
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10864500
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Filing Dt:
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06/10/2004
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Publication #:
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Pub Dt:
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12/15/2005
| | | | |
Title:
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REDUCED POWER PROGRAMMING OF NON-VOLATILE CELLS
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Patent #:
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Issue Dt:
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08/22/2006
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Application #:
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10916413
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Filing Dt:
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08/12/2004
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Publication #:
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Pub Dt:
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02/16/2006
| | | | |
Title:
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DYNAMIC MATCHING OF SIGNAL PATH AND REFERENCE PATH FOR SENSING
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Patent #:
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Issue Dt:
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08/05/2008
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Application #:
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10928665
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Filing Dt:
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08/27/2004
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Title:
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SEMICONDUCTOR COMPONENT HAVING A CONTACT STRUCTURE AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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11/13/2007
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Application #:
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10958044
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Filing Dt:
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10/04/2004
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Title:
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MEMORY DEVICE WITH A SELF-ASSEMBLED POLYMER FILM AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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10961398
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Filing Dt:
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10/12/2004
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Publication #:
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Pub Dt:
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03/27/2008
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Title:
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NROM FABRICATION METHOD
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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10976876
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Filing Dt:
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11/01/2004
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Title:
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SEMICONDUCTOR DEVICE WITH ELECTRICALLY BIASED DIE EDGE SEAL
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Patent #:
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Issue Dt:
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12/25/2012
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10986799
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Filing Dt:
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11/15/2004
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Publication #:
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Pub Dt:
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08/11/2005
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Title:
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A SYSTEM AND METHOD FOR REGULATING LOADING ON AN INTEGRATED CIRCUIT POWER SUPPLY
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Patent #:
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Issue Dt:
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06/19/2007
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10988239
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Filing Dt:
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11/12/2004
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Title:
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UTILIZATION OF A TA-CONTAINING CAP OVER COPPER TO FACILITATE CONCURRENT FORMATION OF COPPER VIAS AND MEMORY ELEMENT STRUCTURES
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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11003574
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Filing Dt:
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12/03/2004
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Title:
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METHOD FOR FORMING WORDLINES HAVING IRREGULAR SPACING IN A MEMORY ARRAY
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Patent #:
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Issue Dt:
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08/14/2007
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11007332
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12/09/2004
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Publication #:
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Pub Dt:
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06/15/2006
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Title:
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METHOD FOR READING NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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11021681
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Filing Dt:
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12/23/2004
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Title:
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MEMORY ELEMENTS USING ORGANIC ACTIVE LAYER
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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11024750
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Filing Dt:
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12/30/2004
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Pub Dt:
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06/02/2005
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Title:
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MULTIPLE USE MEMORY CHIP
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Patent #:
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03/13/2007
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11029380
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01/06/2005
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Pub Dt:
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06/02/2005
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Title:
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METHOD FOR OPERATING A MEMORY DEVICE
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08/01/2006
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Application #:
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11033653
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01/12/2005
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Title:
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USE OF TA-CAPPED METAL LINE TO IMPROVE FORMATION OF MEMORY ELEMENT FILMS
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Patent #:
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Issue Dt:
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07/25/2006
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11057143
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02/15/2005
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Pub Dt:
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06/23/2005
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Title:
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VOLTAGE DETECTION CIRCUIT, SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING VOLTAGE DETECTION CIRCUIT
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Issue Dt:
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12/11/2007
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11063138
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02/22/2005
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Title:
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MEMORY CELL AND METHOD OF MAKING THE MEMORY CELL
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Issue Dt:
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09/12/2006
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11066484
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02/28/2005
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06/30/2005
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Title:
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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING DATA FROM SEMICONDUCTOR MEMORY DEVICE
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12/13/2005
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11085133
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03/22/2005
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Pub Dt:
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07/28/2005
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Title:
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NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH STORES TWO BITS PER MEMORY CELL
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02/20/2007
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11085496
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03/22/2005
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Publication #:
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Pub Dt:
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07/28/2005
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Title:
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NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH A PLURALITY OF SECTORS
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03/27/2007
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11087793
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03/23/2005
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Title:
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ALUMINUM OXIDE AS LINER OR COVER LAYER TO SPACERS IN MEMORY DEVICE
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06/19/2007
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11099660
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04/06/2005
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Pub Dt:
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10/12/2006
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Title:
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ON/OFF CHARGE PUMP
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Issue Dt:
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03/04/2008
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11103367
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04/11/2005
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10/12/2006
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Title:
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THRESHOLD VOLTAGE SHIFT IN NROM CELLS
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Issue Dt:
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08/17/2010
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Application #:
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11110165
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Filing Dt:
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04/20/2005
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Title:
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ORDERED POROSITY TO DIRECT MEMORY ELEMENT FORMATION
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Patent #:
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Issue Dt:
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03/16/2010
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Application #:
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11128389
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05/13/2005
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Title:
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SYSTEM AND METHOD FOR IMPROVING OXIDE-NITRIDE-OXIDE (ONO) COUPLING IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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11155252
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Filing Dt:
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06/17/2005
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Publication #:
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Pub Dt:
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12/21/2006
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Title:
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METHOD CIRCUIT AND SYSTEM FOR COMPENSATING FOR TEMPERATURE INDUCED MARGIN LOSS IN NON-VOLATILE MEMORY CELLS
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Issue Dt:
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04/10/2007
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11165330
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06/24/2005
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Title:
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METHOD OF FORMING A MEMORY DEVICE HAVING IMPROVED ERASE SPEED
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Issue Dt:
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09/20/2011
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11169747
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06/30/2005
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09/28/2006
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Title:
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COMMUNICATION DATA CONTROLLER
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07/25/2006
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11170183
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06/30/2005
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Publication #:
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11/17/2005
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Title:
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FLASH MEMORY HAVING SPARE SECTOR WITH SHORTENED ACCESS TIME
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08/28/2007
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11173257
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07/01/2005
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02/01/2007
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Title:
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USE OF SUPERCRITICAL FLUID TO DRY WAFER AND CLEAN LENS IN IMMERSION LITHOGRAPHY
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01/08/2008
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11175801
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07/05/2005
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01/12/2006
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Title:
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PROTECTION OF NROM DEVICES FROM CHARGE DAMAGE
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Issue Dt:
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06/24/2014
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11189765
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07/27/2005
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Title:
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System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device
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01/01/2008
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11192691
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07/29/2005
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Title:
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AUTOMATED CONTROL THREAD DETERMINATION BASED UPON POST-PROCESS CONSIDERATION
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10/17/2006
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11194394
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08/01/2005
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Pub Dt:
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01/26/2006
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Title:
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OPERATING ARRAY CELLS WITH MATCHED REFERENCE CELLS
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Issue Dt:
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07/10/2007
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11205411
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08/17/2005
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Pub Dt:
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06/15/2006
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Title:
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METHOD FOR READING NON-VOLATILE MEMORY CELLS
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02/23/2010
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11205716
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08/17/2005
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Pub Dt:
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02/22/2007
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Title:
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METHOD OF ERASING NON-VOLATILE MEMORY CELLS
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02/14/2012
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11220872
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09/06/2005
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Publication #:
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Pub Dt:
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03/15/2007
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Title:
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METHOD AND CIRCUIT FOR ERASING A NON-VOLATILE MEMORY CELL
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Issue Dt:
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11/13/2007
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11229664
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Filing Dt:
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09/20/2005
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Publication #:
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Pub Dt:
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03/22/2007
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Title:
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FLASH MEMORY PROGRAMMING USING AN INDICATION BIT TO INTERPRET STATE
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Issue Dt:
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04/19/2011
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11235214
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09/27/2005
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Publication #:
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Pub Dt:
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03/29/2007
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Title:
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METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
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04/10/2007
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11236359
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09/27/2005
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Publication #:
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Pub Dt:
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03/29/2007
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Title:
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DIODE STACK HIGH VOLTAGE REGULATOR
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05/22/2007
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11236360
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09/27/2005
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03/29/2007
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Title:
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METHOD AND APPARATUS FOR MEASURING CHARGE PUMP OUTPUT CURRENT
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04/27/2010
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11240468
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10/03/2005
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Pub Dt:
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04/05/2007
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Title:
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CONTACT SPACER FORMATION USING ATOMIC LAYER DEPOSITION
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06/15/2010
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11246193
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10/11/2005
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07/13/2006
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MULTIPLE USE MEMORY CHIP
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10/30/2007
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11251291
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10/14/2005
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Title:
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05/14/2013
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11259874
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10/26/2005
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05/11/2006
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Title:
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NON-VOLATILE MEMORY DEVICE
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07/31/2007
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11290001
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11/30/2005
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09/28/2006
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12/23/2008
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11290787
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11/30/2005
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Title:
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04/01/2008
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11324718
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01/03/2006
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07/05/2007
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Title:
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METHOD, SYSTEM, AND CIRCUIT FOR OPERATING A NON-VOLATILE MEMORY ARRAY
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09/02/2008
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11328015
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01/09/2006
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06/15/2006
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Title:
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METHOD, SYSTEM, AND CIRCUIT FOR OPERATING A NON-VOLATILE MEMORY ARRAY
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05/06/2008
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11335318
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01/19/2006
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07/20/2006
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Title:
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METHOD, CIRCUIT AND SYSTEMS FOR ERASING ONE OR MORE NON-VOLATILE MEMORY CELLS
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12/23/2008
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11335321
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01/19/2006
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07/20/2006
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PARTIAL ERASE VERIFY
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11/24/2009
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11356267
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02/16/2006
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08/28/2012
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11357081
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02/21/2006
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08/23/2007
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CIRCUIT AND METHOD FOR POWERING UP AN INTEGRATED CIRCUIT AND AN INTEGRATED CIRCUIT UTILIZING SAME
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11/08/2011
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11373932
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03/13/2006
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09/21/2006
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CONTACT IN PLANAR NROM TECHNOLOGY
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07/22/2008
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04/10/2006
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10/11/2007
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06/08/2010
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04/24/2006
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11/24/2009
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04/25/2006
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03/31/2009
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11413962
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04/27/2006
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11/30/2006
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METHOD FOR PROGRAMMING A REFERENCE CELL
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12/29/2009
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05/24/2006
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09/21/2006
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NON-VOLATILE MEMORY STRUCTURE AND METHOD OF FABRICATION
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07/20/2010
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08/02/2006
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08/23/2007
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NROM NON-VOLATILE MEMORY AND MODE OF OPERATION
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04/06/2010
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11462011
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08/02/2006
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08/23/2007
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05/12/2009
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11464253
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08/14/2006
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12/21/2006
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09/28/2010
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11489237
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07/18/2006
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03/01/2007
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08/31/2010
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07/18/2006
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03/08/2007
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12/16/2008
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11490539
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07/19/2006
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07/26/2007
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DYNAMIC MATCHING OF SIGNAL PATH AND REFERENCE PATH FOR SENSING
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07/29/2008
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11497078
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08/01/2006
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11/23/2006
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NON-VOLATILE MEMORY CELL AND NON-VOLATILE MEMORY DEVICES
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01/15/2008
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11497597
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08/02/2006
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02/14/2008
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RAMP GATE ERASE FOR DUAL BIT FLASH MEMORY
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09/19/2017
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08/23/2006
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04/20/2010
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11518192
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09/11/2006
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11/01/2007
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METHOD FOR PROGRAMMING A REFERENCE CELL
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01/10/2012
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09/14/2006
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08/31/2010
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09/08/2006
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03/13/2008
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DUAL STORAGE NODE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
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11/09/2010
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11551390
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10/20/2006
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04/24/2008
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PLANARIZATION METHOD USING HYBRID OXIDE AND POLYSILICON CMP
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11/25/2008
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11580995
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10/16/2006
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06/14/2007
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03/09/2010
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05/24/2007
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10/20/2009
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11/21/2006
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04/24/2008
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09/08/2009
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12/01/2006
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06/14/2007
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02/14/2012
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12/20/2006
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06/26/2008
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05/29/2012
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06/26/2008
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05/29/2012
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12/20/2006
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05/08/2008
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MULTIPLE STAKEHOLDER SECURE MEMORY PARTITIONING AND ACCESS CONTROL
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