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08/07/2012
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Application #:
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11625158
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Filing Dt:
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01/19/2007
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Publication #:
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Pub Dt:
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07/24/2008
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Title:
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BYTE MASK COMMAND FOR MEMORIES
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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11639667
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Filing Dt:
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12/15/2006
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Title:
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SELF-ALIGNED STI WITH SINGLE POLY FOR MANUFACTURING A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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07/29/2014
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Application #:
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11641647
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Filing Dt:
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12/19/2006
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Pub Dt:
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06/19/2008
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Title:
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Method of depositing copper using physical vapor deposition
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Patent #:
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Issue Dt:
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10/05/2010
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Application #:
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11646395
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Filing Dt:
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12/28/2006
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Pub Dt:
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07/12/2007
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Title:
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SECONDARY INJECTION FOR NROM
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Patent #:
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Issue Dt:
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12/29/2009
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Application #:
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11646430
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Filing Dt:
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12/28/2006
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Pub Dt:
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08/30/2007
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Title:
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DOUBLE DENSITY NROM WITH NITRIDE STRIPS (DDNS)
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Patent #:
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09/21/2010
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11687487
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03/16/2007
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09/18/2008
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Title:
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STATE CHANGE SENSING
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06/22/2010
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11704908
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02/12/2007
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07/19/2007
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Title:
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MEMORY ARRAY PROGRAMMING CIRCUIT AND A METHOD FOR USING THE CIRCUIT
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Patent #:
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Issue Dt:
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07/15/2008
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11785285
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Filing Dt:
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04/17/2007
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Publication #:
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Pub Dt:
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09/06/2007
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Title:
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NON-VOLATILE MEMORY CELL AND NON-VOLATILE MEMORY DEVICE USING SAID CELL
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Patent #:
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02/12/2013
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11796073
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04/26/2007
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Publication #:
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Pub Dt:
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10/30/2008
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Title:
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MEMORY DEVICE WITH IMPROVED PERFORMANCE
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Patent #:
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Issue Dt:
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05/19/2009
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11822777
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Filing Dt:
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07/10/2007
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Publication #:
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Pub Dt:
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01/03/2008
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Title:
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NON-VOLATILE MEMORY DEVICE AND METHOD FOR READING CELLS
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Patent #:
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Issue Dt:
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05/19/2009
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11834420
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Filing Dt:
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08/06/2007
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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READING MULTI-CELL MEMORY DEVICES UTILIZING COMPLEMENTARY BIT INFORMATION
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Patent #:
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Issue Dt:
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04/07/2009
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11841468
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08/20/2007
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02/26/2009
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Title:
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CMOS LOGIC COMPATIBLE NON-VOLATILE MEMORY CELL STRUCTURE, OPERATION, AND ARRAY CONFIGURATION
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03/11/2014
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09/10/2007
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03/12/2009
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Title:
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CRYPTOGRAPHIC SYSTEM WITH MODULAR RANDOMIZATION OF EXPONENTIATION
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03/20/2012
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11870102
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10/10/2007
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Pub Dt:
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04/16/2009
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Title:
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RANDOMIZED RSA-BASED CRYPTOGRAPHIC EXPONENTIATION RESISTANT TO SIDE CHANNEL AND FAULT ATTACKS
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08/07/2012
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11928434
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10/30/2007
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04/30/2009
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Title:
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ERROR CORRECTION CODING IN FLASH MEMORY DEVICES
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07/10/2012
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11949521
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12/03/2007
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06/04/2009
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Title:
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DIRECT INTERCONNECTION BETWEEN PROCESSOR AND MEMORY COMPONENT
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03/20/2012
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11957226
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12/14/2007
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06/18/2009
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Title:
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INTELLIGENT MEMORY DATA MANAGEMENT
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02/14/2012
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11958254
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12/17/2007
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06/26/2008
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Title:
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INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM
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Patent #:
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09/15/2009
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11958425
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Filing Dt:
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12/18/2007
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Publication #:
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Pub Dt:
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06/18/2009
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Title:
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FLASH MEMORY WITH OPTIMIZED WRITE SECTOR SPARES
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Patent #:
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09/04/2012
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11963078
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12/21/2007
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Pub Dt:
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06/25/2009
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Title:
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SYSTEM AND METHOD FOR OPTIMIZED ERROR CORRECTION IN FLASH MEMORY ARRAYS
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08/11/2009
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11979182
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10/31/2007
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Pub Dt:
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06/05/2008
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Title:
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MULTIPLE USE MEMORY CHIP
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Patent #:
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01/31/2012
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11979183
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10/31/2007
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05/01/2008
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Title:
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NROM FRABRICATION METHOD
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02/10/2009
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11979184
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10/31/2007
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Pub Dt:
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05/29/2008
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Title:
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MULTIPLE USE MEMORY CHIP
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10/12/2010
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11979313
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11/01/2007
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06/05/2008
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Title:
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FORMING SILICON TRENCH ISOLATION (STI) IN SEMICONDUCTOR DEVICES SELF-ALIGNED TO DIFFUSION
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12/07/2010
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11987003
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11/26/2007
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06/12/2008
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PLL CIRCUIT
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08/30/2011
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12005323
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12/27/2007
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06/12/2008
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01/22/2013
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03/14/2008
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09/17/2009
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USING LPDDR1 BUS AS TRANSPORT LAYER TO COMMUNICATE TO FLASH
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06/04/2013
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03/31/2008
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10/01/2009
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FLASH MEMORY AND OPERATING SYSTEM KERNEL
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05/11/2010
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12071749
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02/26/2008
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07/31/2008
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10/06/2009
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04/14/2008
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08/21/2008
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REDUCED POWER PROGRAMMING OF NON-VOLATILE CELLS
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06/22/2010
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12087594
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07/10/2008
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01/01/2009
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02/21/2012
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06/11/2008
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06/11/2009
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02/19/2013
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06/12/2008
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06/11/2009
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01/04/2011
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09/17/2008
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03/19/2009
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01/17/2012
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12232437
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09/17/2008
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03/19/2009
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PRE-CHARGE SENSING SCHEME FOR NON-VOLATILE MEMORY (NVM)
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01/04/2011
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12232495
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09/18/2008
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04/16/2009
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METHOD, DEVICE AND SYSTEM FOR REGULATING ACCESS TO AN INTEGRATED CIRCUIT (IC) DEVICE
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12258131
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10/24/2008
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05/07/2009
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
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12/07/2010
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11/25/2008
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05/27/2010
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SPI ADDRESSING BEYOND 24-BITS
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12/25/2012
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11/03/2008
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08/13/2009
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NON BINARY FLASH ARRAY ARCHITECTURE AND METHOD OF OPERATION
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02/21/2012
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11/07/2008
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05/07/2009
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04/12/2011
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12292240
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11/14/2008
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05/14/2009
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01/04/2011
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11/24/2008
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09/17/2009
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09/11/2012
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02/23/2009
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12/31/2009
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METHODS, CIRCUITS AND SYSTEMS FOR READING NON-VOLATILE MEMORY CELLS
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05/29/2012
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01/08/2009
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07/09/2009
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RETENTION IN NVM WITH TOP OR BOTTOM INJECTION
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06/26/2012
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01/08/2009
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08/13/2009
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NON-VOLATILE MEMORY CELL WITH INJECTOR
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05/17/2011
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11/25/2008
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09/10/2009
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05/29/2012
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02/25/2009
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12/24/2009
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POWER-ON DETECTION CIRCUIT AND MICROCONTROLLER
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11/13/2012
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03/24/2009
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08/27/2009
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TRANSMITTING/RECEIVING SYSTEM, NODE AND COMMUNICATION METHOD
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08/14/2012
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12/23/2009
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06/23/2011
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12/04/2012
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12/23/2009
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06/23/2011
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06/21/2011
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12/10/2009
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07/08/2010
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NON-VOLATILE MEMORY STRUCTURE AND METHOD OF FABRICATION
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11/05/2013
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02/01/2010
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08/05/2010
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CHARGING CIRCUIT, CHARGING APPARATUS, ELECTRONIC EQUIPMENT AND CHARGING METHOD
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10/16/2012
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03/23/2010
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09/29/2011
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VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
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01/11/2011
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04/22/2010
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08/12/2010
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07/16/2013
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06/17/2010
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12/23/2010
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TIMING CONTROLLER, TIMING CONTROL METHOD, AND TIMING CONTROL SYSTEM
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07/05/2011
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09/21/2010
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01/13/2011
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PLANARIZATION METHOD USING HYBRID OXIDE AND POLYSILICON CMP
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10/02/2012
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11/01/2010
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02/24/2011
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PLL CIRCUIT
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02/12/2013
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12926718
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12/07/2010
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06/09/2011
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METHODS CIRCUITS DEVICES AND SYSTEMS FOR OPERATING AN ARRAY OF NON-VOLATILE MEMORY CELLS
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01/21/2014
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03/23/2011
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10/20/2011
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DATA WRITING METHOD AND SYSTEM
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11/26/2013
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11/22/2011
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03/15/2012
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PRE-CHARGE SENSING SCHEME FOR NON-VOLATILE MEMORY (NVM)
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