Total properties:
279
Page
3
of
3
Pages:
1 2 3
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2020
|
Application #:
|
16220489
|
Filing Dt:
|
12/14/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
CIRCUITS, APPARATUSES, AND METHODS FOR FREQUENCY DIVISION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2020
|
Application #:
|
16220491
|
Filing Dt:
|
12/14/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
ERROR CORRECTION CODE (ECC) OPERATIONS IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2020
|
Application #:
|
16220755
|
Filing Dt:
|
12/14/2018
|
Publication #:
|
|
Pub Dt:
|
06/18/2020
| | | | |
Title:
|
FEEDBACK FOR MULTI-LEVEL SIGNALING IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2019
|
Application #:
|
16220912
|
Filing Dt:
|
12/14/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
APPARATUS AND METHODS FOR IN DATA PATH COMPUTE OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2020
|
Application #:
|
16221233
|
Filing Dt:
|
12/14/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
SCAN CHAIN OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2020
|
Application #:
|
16221846
|
Filing Dt:
|
12/17/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
UNALIGNED DATA COALESCING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
16222160
|
Filing Dt:
|
12/17/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
RESPONDING TO POWER LOSS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
16223162
|
Filing Dt:
|
12/18/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
OBFUSCATION-ENHANCED MEMORY ENCRYPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2021
|
Application #:
|
16223352
|
Filing Dt:
|
12/18/2018
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
Title:
|
APPARATUSES AND METHOD FOR OVER-VOLTAGE EVENT PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2021
|
Application #:
|
16223897
|
Filing Dt:
|
12/18/2018
|
Publication #:
|
|
Pub Dt:
|
06/18/2020
| | | | |
Title:
|
MANAGEMENT OF EVENT LOG INFORMATION OF A MEMORY SUB-SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2020
|
Application #:
|
16224498
|
Filing Dt:
|
12/18/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
APPARATUSES AND METHODS FOR MEMORY DEVICE AS A STORE FOR BLOCK PROGRAM INSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2021
|
Application #:
|
16224588
|
Filing Dt:
|
12/18/2018
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
Title:
|
APPARATUSES AND METHODS FOR SHIFT DECISIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2021
|
Application #:
|
16225036
|
Filing Dt:
|
12/19/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
APPARATUS AND METHODS FOR PROGRAMMING MEMORY CELLS RESPONSIVE TO AN INDICATION OF AGE OF THE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2020
|
Application #:
|
16225303
|
Filing Dt:
|
12/19/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
MEMORY DEVICE WITH WRITE DATA BUS CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2020
|
Application #:
|
16225678
|
Filing Dt:
|
12/19/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
APPARATUSES AND METHODS FOR TEMPERATURE INDEPENDENT OSCILLATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2020
|
Application #:
|
16226282
|
Filing Dt:
|
12/19/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
POWER LOSS PROTECTION IN MEMORY SUB-SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2020
|
Application #:
|
16226433
|
Filing Dt:
|
12/19/2018
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
Title:
|
MEMORY DEVICE WITH A COMMON SOURCE SELECT LINE FOR TWO MEMORY PORTIONS OF A LOGIC SECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2020
|
Application #:
|
16226476
|
Filing Dt:
|
12/19/2018
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
Title:
|
PROGRAMMING NON-VOLATILE ELECTRONIC MEMORY DEVICE WITH NAND ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2020
|
Application #:
|
16226525
|
Filing Dt:
|
12/19/2018
|
Title:
|
APPARATUSES AND METHODS FOR MULTI-BANK REFRESH TIMING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2020
|
Application #:
|
16226626
|
Filing Dt:
|
12/19/2018
|
Publication #:
|
|
Pub Dt:
|
10/31/2019
| | | | |
Title:
|
CROSS POINT ARRAY MEMORY IN A NON-VOLATILE DUAL IN-LINE MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2022
|
Application #:
|
16227072
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
LOW COST AND LOW LATENCY LOGICAL UNIT ERASE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2020
|
Application #:
|
16227339
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
PERSISTENT CONTENT IN NONVOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2020
|
Application #:
|
16227375
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
APPARATUSES AND METHODS FOR SENSING A PHASE-CHANGE TEST CELL AND DETERMINING CHANGES TO THE TEST CELL RESISTANCE DUE TO THERMAL EXPOSURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2023
|
Application #:
|
16227393
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
DEGRADATION SIGNALING FOR A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2021
|
Application #:
|
16227492
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
DEVICES INCLUDING CONDUCTIVE INTERCONNECT STRUCTURES, RELATED ELECTRONIC SYSTEMS, AND RELATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2020
|
Application #:
|
16227874
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
ASYMMETRICAL MULTI-GATE STRING DRIVER FOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2020
|
Application #:
|
16228072
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
06/27/2019
| | | | |
Title:
|
CELL DISTURB PREVENTION USING A LEAKER DEVICE TO REDUCE EXCESS CHARGE FROM AN ELECTRONIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2019
|
Application #:
|
16228156
|
Filing Dt:
|
12/20/2018
|
Title:
|
APPARATUSES AND METHODS INCLUDING CONFIGURABLE LOGIC CIRCUITS AND LAYOUT THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
16228203
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
SECURE COMMUNICATION FOR LOG REPORTING IN MEMORY SUB-SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2022
|
Application #:
|
16228336
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
USING A SECOND CONTENT-ADDRESSABLE MEMORY TO MANAGE MEMORY BURST ACCESSES IN MEMORY SUB-SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2022
|
Application #:
|
16228377
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2020
|
Application #:
|
16228387
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
BAD BLOCK MANAGEMENT FOR MEMORY SUB-SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2022
|
Application #:
|
16228428
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
Title:
|
APPARATUSES AND METHODS USING NEGATIVE VOLTAGES IN PART OF MEMORY WRITE, READ, AND ERASE OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2020
|
Application #:
|
16228534
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
Title:
|
3D MEMORY DEVICE INCLUDING SHARED SELECT GATE CONNECTIONS BETWEEN MEMORY BLOCKS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2020
|
Application #:
|
16228574
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
MEMORY DEVICE INCLUDING PASS TRANSISTORS IN MEMORY TIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2021
|
Application #:
|
16228632
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
CHANGING OF ERROR CORRECTION CODES BASED ON THE WEAR OF A MEMORY SUB-SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2019
|
Application #:
|
16228733
|
Filing Dt:
|
12/20/2018
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
Title:
|
APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN 3D NON-VOLATILE MEMORY OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2022
|
Application #:
|
16229044
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
08/29/2019
| | | | |
Title:
|
ARTIFICIAL NEURAL NETWORK INTEGRITY VERIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2023
|
Application #:
|
16229151
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
SOLID STATE LIGHTING DEVICES WITH IMPROVED CURRENT SPREADING AND LIGHT EXTRACTION AND ASSOCIATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2019
|
Application #:
|
16229214
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
04/18/2019
| | | | |
Title:
|
INPUT BUFFER CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2020
|
Application #:
|
16229257
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2021
|
Application #:
|
16229266
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
06/06/2019
| | | | |
Title:
|
APPARATUSES AND METHODS FOR PROVIDING BIAS SIGNALS IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2020
|
Application #:
|
16229578
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
04/18/2019
| | | | |
Title:
|
SELF-ACCUMULATING EXCLUSIVE OR PROGRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2021
|
Application #:
|
16229609
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
MONOTONIC COUNTERS IN MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2022
|
Application #:
|
16229677
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
RECYCLED VERSION NUMBER VALUES IN FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2020
|
Application #:
|
16230251
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
OPTIMIZED SCAN INTERVAL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2020
|
Application #:
|
16230299
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
MANAGEMENT OF POWER STATE TRANSITIONS OF A MEMORY SUB-SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2022
|
Application #:
|
16230382
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
04/23/2020
| | | | |
Title:
|
Memory Arrays And Methods Used In Forming A Memory Array
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2023
|
Application #:
|
16230699
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A REDUCED FOOTPRINT OF WIRES CONNECTING A DLL CIRCUIT WITH AN INPUT/OUTPUT BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2020
|
Application #:
|
16231081
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
HOLDUP SELF-TESTS FOR POWER LOSS OPERATIONS ON MEMORY SYSTEMS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
16231267
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
MEMORY DEVICE AND MANAGED MEMORY SYSTEM WITH WIRELESS DEBUG COMMUNICATION PORT AND METHODS FOR OPERATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2023
|
Application #:
|
16231308
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
06/25/2020
| | | | |
Title:
|
Data Integrity Protection for Relocating Data in a Memory System
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2021
|
Application #:
|
16231327
|
Filing Dt:
|
12/21/2018
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
Title:
|
APPARATUSES AND METHODS FOR SELECTIVE ROW REFRESHES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2020
|
Application #:
|
16232634
|
Filing Dt:
|
12/26/2018
|
Title:
|
Construction Of Integrated Circuitry, DRAM Circuitry, A Method Of Forming A Conductive Line Construction, A Method Of Forming Memory Circuitry, And A Method Of Forming DRAM Circuitry
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2021
|
Application #:
|
16232837
|
Filing Dt:
|
12/26/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
APPARATUSES AND METHODS FOR DISTRIBUTED TARGETED REFRESH OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2020
|
Application #:
|
16234208
|
Filing Dt:
|
12/27/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL CONFIGURABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
16234319
|
Filing Dt:
|
12/27/2018
|
Publication #:
|
|
Pub Dt:
|
08/22/2019
| | | | |
Title:
|
Apparatuses Having Memory Strings Compared to One Another Through a Sense Amplifier
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2020
|
Application #:
|
16235066
|
Filing Dt:
|
12/28/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
MEMORY CELLS CONFIGURED TO GENERATE WEIGHTED INPUTS FOR NEURAL NETWORKS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2021
|
Application #:
|
16235163
|
Filing Dt:
|
12/28/2018
|
Publication #:
|
|
Pub Dt:
|
09/12/2019
| | | | |
Title:
|
PSEUDO-NON-VOLATILE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2021
|
Application #:
|
16235474
|
Filing Dt:
|
12/28/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
INTERRUPTION OF PROGRAM OPERATIONS AT A MEMORY SUB-SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2020
|
Application #:
|
16235497
|
Filing Dt:
|
12/28/2018
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
Title:
|
Memory Systems and Memory Programming Methods
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2021
|
Application #:
|
16235645
|
Filing Dt:
|
12/28/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
APPARATUSES AND METHODS FOR ARRANGING THROUGH-SILICON VIAS AND PADS IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
16235951
|
Filing Dt:
|
12/28/2018
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
Title:
|
APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2020
|
Application #:
|
16235957
|
Filing Dt:
|
12/28/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
METHODS OF FORMING AN APPARATUS, AND RELATED APPARATUSES AND ELECTRONIC SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2022
|
Application #:
|
16236005
|
Filing Dt:
|
12/28/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
PHYSICAL UNCLONABLE FUNCTION WITH NAND MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2020
|
Application #:
|
16236100
|
Filing Dt:
|
12/28/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
ELECTRICAL DEVICE WITH TEST PADS ENCASED WITHIN THE PACKAGING MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2022
|
Application #:
|
16236785
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
RESET INTERCEPTION TO AVOID DATA LOSS IN STORAGE DEVICE RESETS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2021
|
Application #:
|
16236897
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
Title:
|
Namespace Change Propagation in Non-Volatile Memory Devices
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2020
|
Application #:
|
16236922
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
04/30/2020
| | | | |
Title:
|
PROVIDING INFORMATION FOR A CONTROLLER MEMORY BUFFER ELASTICITY STATUS OF A MEMORY SUB-SYSTEM TO A HOST SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2021
|
Application #:
|
16236928
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
FILE CREATION WITH REQUESTER-SPECIFIED BACKING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2021
|
Application #:
|
16237104
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
BINARY PARALLEL ADDER AND MULTIPLIER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2020
|
Application #:
|
16237134
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2021
|
Application #:
|
16237250
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
USING A COMMON POOL OF BLOCKS FOR USER DATA AND A SYSTEM DATA STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2020
|
Application #:
|
16237263
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
07/02/2020
| | | | |
Title:
|
METHODS AND SYSTEM WITH DYNAMIC ECC VOLTAGE AND FREQUENCY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2020
|
Application #:
|
16237287
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
07/11/2019
| | | | |
Title:
|
MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2020
|
Application #:
|
16237337
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
09/12/2019
| | | | |
Title:
|
APPARATUS AND METHODS INCLUDING SOURCE GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2020
|
Application #:
|
16237346
|
Filing Dt:
|
12/31/2018
|
Publication #:
|
|
Pub Dt:
|
09/12/2019
| | | | |
Title:
|
APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUB-BLOCKS OF MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2020
|
Application #:
|
16238653
|
Filing Dt:
|
01/03/2019
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
Title:
|
Memory Cell, An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor With The Array Comprising Rows Of Access Lines And Columns Of Digit Lines, A 2T-1C Memory Cell, And Methods Of Forming An Array Of Capacitors And Access Transistors There-Above
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
16238689
|
Filing Dt:
|
01/03/2019
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
Title:
|
Arrays Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor, Methods Of Forming A Tier Of An Array Of Memory Cells, And Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor
|
|