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Patent #:
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Issue Dt:
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01/19/2010
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Application #:
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11556833
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Filing Dt:
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11/06/2006
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Publication #:
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Pub Dt:
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05/29/2008
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Title:
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SEMICONDUCTOR STRUCTURES INCORPORATING MULTIPLE CRYSTALLOGRAPHIC PLANES AND METHODS FOR FABRICATION THEREOF
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Patent #:
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Issue Dt:
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01/10/2012
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Application #:
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11558842
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Filing Dt:
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11/10/2006
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Publication #:
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Pub Dt:
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05/15/2008
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Title:
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AIR/FLUID COOLING SYSTEM
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Patent #:
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Issue Dt:
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08/04/2009
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Application #:
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11560044
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Filing Dt:
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11/15/2006
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Publication #:
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Pub Dt:
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05/15/2008
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Title:
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INTERCONNECT STRUCTURE HAVING ENHANCED ELECTROMIGRATION RELIABILTY AND A METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
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06/08/2010
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Application #:
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11608591
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Filing Dt:
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12/08/2006
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Publication #:
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Pub Dt:
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11/01/2007
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Title:
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A SEMICONDUCTOR DEVICE HAVING STRESSED ETCH STOP LAYERS OF DIFFERENT INTRINSIC STRESS IN COMBINATION WITH PN JUNCTIONS OF DIFFERENT DESIGN IN DIFFERENT DEVICE REGIONS
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Patent #:
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Issue Dt:
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09/22/2009
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Application #:
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11615080
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Filing Dt:
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12/22/2006
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Publication #:
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Pub Dt:
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11/15/2007
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Title:
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RECIRCULATION AND REUSE OF DUMMY DISPENSED RESIST
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Patent #:
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Issue Dt:
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04/13/2010
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Application #:
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11618974
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Filing Dt:
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01/02/2007
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Publication #:
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Pub Dt:
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07/03/2008
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Title:
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METHOD FOR CO-ALIGNMENT OF MIXED OPTICAL AND ELECTRON BEAM LITHOGRAPHIC FABRICATION LEVELS
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Patent #:
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Issue Dt:
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09/22/2009
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Application #:
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11619235
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Filing Dt:
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01/03/2007
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Publication #:
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Pub Dt:
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12/06/2007
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Title:
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METALLIZATION LAYER OF A SEMICONDUCTOR DEVICE HAVING DIFFERENTLY THICK METAL LINES AND A METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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04/21/2009
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Application #:
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11619357
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Filing Dt:
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01/03/2007
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Publication #:
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Pub Dt:
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07/03/2008
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Title:
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DUAL STRESS STI
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Patent #:
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Issue Dt:
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02/09/2010
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Application #:
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11620406
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Filing Dt:
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01/05/2007
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Publication #:
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Pub Dt:
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12/06/2007
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Title:
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METHOD OF INCREASING TRANSISTOR DRIVE CURRENT BY RECESSING AN ISOLATION TRENCH
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Patent #:
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Issue Dt:
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07/27/2010
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Application #:
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11623372
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Filing Dt:
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01/16/2007
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Publication #:
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Pub Dt:
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12/27/2007
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Title:
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TEST STRUCTURE FOR MONITORING LEAKAGE CURRENTS IN A METALLIZATION LAYER
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Patent #:
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Issue Dt:
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05/18/2010
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Application #:
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11624436
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Filing Dt:
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01/18/2007
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Publication #:
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Pub Dt:
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07/24/2008
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Title:
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CHIP CARRIER SUBSTRATE CAPACITOR AND METHOD FOR FABRICATION THEREOF
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Patent #:
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Issue Dt:
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07/05/2011
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Application #:
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11625576
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Filing Dt:
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01/22/2007
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Publication #:
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Pub Dt:
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07/24/2008
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Title:
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HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT
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Patent #:
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Issue Dt:
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05/25/2010
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Application #:
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11639865
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Filing Dt:
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12/15/2006
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Publication #:
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Pub Dt:
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06/19/2008
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Title:
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SENSING DEVICE FOR FLOATING BODY CELL MEMORY AND METHOD THEREOF
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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11653975
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Filing Dt:
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01/17/2007
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Publication #:
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Pub Dt:
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05/24/2007
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Title:
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Live connection enhancement for data source interface
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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11669902
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Filing Dt:
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01/31/2007
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Publication #:
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Pub Dt:
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07/31/2008
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Title:
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STRAINED MOS DEVICES USING SOURCE/DRAIN EPITAXY
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Patent #:
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Issue Dt:
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02/23/2010
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Application #:
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11672109
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Filing Dt:
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02/07/2007
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Publication #:
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Pub Dt:
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08/07/2008
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Title:
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SEMICONDUCTOR STRUCTURE INCLUDING DOPED SILICON CARBON LINER LAYER AND METHOD FOR FABRICATION THEREOF
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Patent #:
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Issue Dt:
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07/27/2010
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Application #:
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11672146
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Filing Dt:
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02/07/2007
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Publication #:
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Pub Dt:
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01/17/2008
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Title:
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TEST STRUCTURE FOR DETERMINING CHARACTERISTICS OF SEMICONDUCTOR ALLOYS IN SOI TRANSISTORS BY X-RAY DIFFRACTION
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Patent #:
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Issue Dt:
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10/06/2009
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Application #:
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11673298
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Filing Dt:
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02/09/2007
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Publication #:
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Pub Dt:
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08/14/2008
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Title:
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SYSTEM AND METHOD FOR GENERATING CONSTRAINT PRESERVING TESTCASES IN THE PRESENCE OF DEAD-END CONSTRAINTS
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Patent #:
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Issue Dt:
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12/28/2010
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Application #:
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11679483
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Filing Dt:
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02/27/2007
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Publication #:
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Pub Dt:
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08/28/2008
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Title:
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STRUCTURE INCLUDING VIA HAVING REFRACTORY METAL COLLAR AT COPPER WIRE AND DIELECTRIC LAYER LINER-LESS INTERFACE AND RELATED METHOD
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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11687731
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Filing Dt:
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03/19/2007
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Publication #:
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Pub Dt:
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07/12/2007
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Title:
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METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS
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Patent #:
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Issue Dt:
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12/08/2009
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Application #:
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11692627
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Filing Dt:
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03/28/2007
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Publication #:
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Pub Dt:
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10/02/2008
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Title:
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MEMORY CELLS, MEMORY DEVICES AND INTEGRATED CIRCUITS INCORPORATING THE SAME
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Patent #:
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Issue Dt:
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09/21/2010
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Application #:
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11697890
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Filing Dt:
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04/09/2007
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Publication #:
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Pub Dt:
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03/06/2008
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Title:
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TRANSISTOR HAVING A LOCALLY PROVIDED METAL SILICIDE REGION IN CONTACT AREAS AND A METHOD OF FORMING THE TRANSISTOR
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Patent #:
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Issue Dt:
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07/07/2009
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Application #:
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11736622
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Filing Dt:
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04/18/2007
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Publication #:
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Pub Dt:
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04/03/2008
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Title:
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FIELD EFFECT TRANSISTOR COMPRISING A STRESSED CHANNEL REGION AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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11737447
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Filing Dt:
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04/19/2007
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Publication #:
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Pub Dt:
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05/24/2012
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Title:
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SYSTEM FOR ABATING THE SIMULTANEOUS FLOW OF SILANE AND ARSINE
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Patent #:
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Issue Dt:
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02/14/2012
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Application #:
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11741898
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Filing Dt:
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04/30/2007
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Publication #:
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Pub Dt:
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10/30/2008
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Title:
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RECESSED GATE CHANNEL WITH LOW VT CORNER
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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11746320
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Filing Dt:
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05/09/2007
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Publication #:
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Pub Dt:
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05/01/2008
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Title:
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METHOD AND SYSTEM FOR RANDOMIZING WAFERS IN A COMPLEX PROCESS LINE
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Patent #:
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Issue Dt:
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06/15/2010
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Application #:
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11750267
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Filing Dt:
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05/17/2007
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Publication #:
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Pub Dt:
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11/20/2008
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Title:
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TECHNIQUES FOR INTEGRATED CIRCUIT CLOCK MANAGEMENT
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Patent #:
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Issue Dt:
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09/29/2009
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Application #:
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11753862
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Filing Dt:
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05/25/2007
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Publication #:
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Pub Dt:
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11/27/2008
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Title:
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HALO-FIRST ULTRA-THIN SOI FET FOR SUPERIOR SHORT CHANNEL CONTROL
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Patent #:
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Issue Dt:
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02/02/2010
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Application #:
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11757472
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Filing Dt:
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06/04/2007
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Publication #:
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Pub Dt:
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12/04/2008
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Title:
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SOI FET WITH SOURCE-SIDE BODY DOPING
|
|
|
|
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Patent #:
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Issue Dt:
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08/24/2010
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Application #:
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11757575
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Filing Dt:
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06/04/2007
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Publication #:
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Pub Dt:
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06/05/2008
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Title:
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SEMICONDUCTOR SUBSTRATE HAVING A PROTECTION LAYER AT THE SUBSTRATE BACK SIDE
|
|
|
|
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Patent #:
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Issue Dt:
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10/13/2009
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Application #:
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11761568
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Filing Dt:
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06/12/2007
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Publication #:
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Pub Dt:
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12/18/2008
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Title:
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PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION
|
|
|
|
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Patent #:
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Issue Dt:
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05/22/2012
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Application #:
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11763781
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Filing Dt:
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06/15/2007
|
|
Publication #:
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Pub Dt:
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10/11/2007
| | | | |
|
Title:
|
SYSTEM AND METHOD TO IMPROVE CHIP YIELD, RELIABILITY AND PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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10/04/2011
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Application #:
|
11764948
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Filing Dt:
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06/19/2007
|
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Publication #:
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Pub Dt:
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12/25/2008
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Title:
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FIELD EFFECT TRANSISTOR INCORPORATING AT LEAST ONE STRUCTURE FOR IMPARTING TEMPERATURE-DEPENDENT STRAIN ON THE CHANNEL REGION AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR
|
|
|
|
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Patent #:
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Issue Dt:
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04/26/2011
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Application #:
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11771854
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
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01/01/2009
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Title:
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POLYMERIC MATERIAL, METHOD OF FORMING THE POLYMERIC MATERIAL, AND METHOD OF FORMING A THIN FILM USING THE POLYMERIC MATERIAL
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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11778045
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Filing Dt:
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07/15/2007
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Publication #:
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Pub Dt:
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01/15/2009
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Title:
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METHODS FOR FORMING SELF-ALIGNED DUAL STRESS LINERS FOR CMOS SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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01/12/2010
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Application #:
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11781854
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Filing Dt:
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07/23/2007
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Publication #:
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Pub Dt:
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01/29/2009
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Title:
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COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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11823056
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Filing Dt:
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06/26/2007
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Publication #:
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Pub Dt:
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01/01/2009
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Title:
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Method for preventing void formation in a solder joint
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Patent #:
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Issue Dt:
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07/06/2010
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Application #:
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11830349
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Filing Dt:
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07/30/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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C4NP SERVO CONTROLLED SOLDER FILL HEAD
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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11831208
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Filing Dt:
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07/31/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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ORIENTATION-INDEPENDENT MULTI-LAYER BEOL CAPACITOR
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|
|
|
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Patent #:
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Issue Dt:
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06/01/2010
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Application #:
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11833143
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Filing Dt:
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08/02/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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PHASE CHANGE MEMORY WITH DUAL WORD LINES AND SOURCE LINES AND METHOD OF OPERATING SAME
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|
|
|
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Patent #:
|
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Issue Dt:
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02/09/2010
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Application #:
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11833354
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Filing Dt:
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08/03/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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PROGRAMMABLE VIA DEVICES WITH AIR GAP ISOLATION
|
|
|
|
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Patent #:
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Issue Dt:
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05/27/2014
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Application #:
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11834641
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Filing Dt:
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08/06/2007
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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FET DEVICE WITH STABILIZED THRESHOLD MODIFYING MATERIAL
|
|
|
|
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
|
11836253
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Filing Dt:
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08/09/2007
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|
Publication #:
|
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Pub Dt:
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02/12/2009
| | | | |
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Title:
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CORRUGATED INTERFACES FOR MULTILAYERED INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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07/28/2009
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Application #:
|
11838941
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Filing Dt:
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08/15/2007
|
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Publication #:
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Pub Dt:
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11/29/2007
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Title:
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SILICON GERMANIUM EMITTER
|
|
|
|
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Patent #:
|
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Issue Dt:
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07/27/2010
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Application #:
|
11843358
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Filing Dt:
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08/22/2007
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Publication #:
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Pub Dt:
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07/31/2008
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Title:
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TRANSISTOR WITH EMBEDDED SILICON/GERMANIUM MATERIAL ON A STRAINED SEMICONDUCTOR ON INSULATOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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11/19/2013
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Application #:
|
11844397
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Filing Dt:
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08/24/2007
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Publication #:
|
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Pub Dt:
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02/26/2009
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Title:
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ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE AND METHOD OF SHIELDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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08/24/2010
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Application #:
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11849908
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Filing Dt:
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09/04/2007
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Publication #:
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Pub Dt:
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01/10/2008
| | | | |
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Title:
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SYSTEM AND METHOD FOR CREATING A STANDARD CELL LIBRARY FOR USE IN CIRCUIT DESIGNS
|
|
|
|
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Patent #:
|
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Issue Dt:
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01/05/2010
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Application #:
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11855979
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Filing Dt:
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09/14/2007
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Publication #:
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Pub Dt:
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03/19/2009
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Title:
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PHASE CHANGE MEMORY CELL IN VIA ARRAY WITH SELF-ALIGNED, SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING
|
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Patent #:
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Issue Dt:
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05/15/2012
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Application #:
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11855983
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Filing Dt:
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09/14/2007
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Publication #:
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Pub Dt:
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03/19/2009
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Title:
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PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING
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Patent #:
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Issue Dt:
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08/31/2010
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Application #:
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11856799
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Filing Dt:
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09/18/2007
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Publication #:
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Pub Dt:
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07/03/2008
| | | | |
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Title:
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INLINE STRESS EVALUATION IN MICROSTRUCTURE DEVICES
|
|
|
|
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Patent #:
|
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Issue Dt:
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12/31/2013
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Application #:
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11858636
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Filing Dt:
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09/20/2007
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Publication #:
|
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Pub Dt:
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03/26/2009
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Title:
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PATTERNABLE DIELECTRIC FILM STRUCTURE WITH IMPROVED LITHOGRAPHY AND METHOD OF FABRICATING SAME
|
|
|
|
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Patent #:
|
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Issue Dt:
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04/20/2010
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Application #:
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11862345
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Filing Dt:
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09/27/2007
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Publication #:
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Pub Dt:
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07/31/2008
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Title:
|
METHOD FOR REDUCING ETCH-INDUCED PROCESS UNIFORMITIES BY OMITTING DEPOSITION OF AN ENDPOINT DETECTION LAYER DURING PATTERNING OF STRESSED OVERLAYERS IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11866502
|
Filing Dt:
|
10/03/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
|
Title:
|
CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
11867840
|
Filing Dt:
|
10/05/2007
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
SIDEWALL SEMICONDUCTOR TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
11872399
|
Filing Dt:
|
10/15/2007
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
|
Title:
|
METHODS FOR FABRICATING DEVICE FEATURES HAVING SMALL DIMENSIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
11874454
|
Filing Dt:
|
10/18/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
|
Title:
|
BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
11874565
|
Filing Dt:
|
10/18/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
|
Title:
|
SEMICONDUCTOR-ON-INSULATOR SUBSTRATE WITH A DIFFUSION BARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
11927073
|
Filing Dt:
|
10/29/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
|
Title:
|
A ROBUST SPECTRAL ANALYZER FOR ONE-DIMENSIONAL AND MULTI-DIMENSIONAL DATA ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
11930236
|
Filing Dt:
|
10/31/2007
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
|
Title:
|
SOLUTION FOR FORMING POLISHING SLURRY, POLISHING SLURRY AND RELATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
11937637
|
Filing Dt:
|
11/09/2007
|
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
|
Title:
|
METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
11940720
|
Filing Dt:
|
11/15/2007
|
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ELECTROPLATING ON SOI AND BULK SEMICONDUCTOR WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
11942400
|
Filing Dt:
|
11/19/2007
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
|
Title:
|
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
11950453
|
Filing Dt:
|
12/05/2007
|
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
|
Title:
|
METHOD OF FORMING A MATERIAL HAVING A PREDEFINED MORPHOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
11951092
|
Filing Dt:
|
12/05/2007
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
|
Title:
|
METHOD FOR PREVENTING THE FORMATION OF ELECTRICAL SHORTS VIA CONTACT ILD VOIDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
11964494
|
Filing Dt:
|
12/26/2007
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
|
Title:
|
TECHNIQUE FOR ENHANCING TRANSISTOR PERFORMANCE BY TRANSISTOR SPECIFIC CONTACT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
11970665
|
Filing Dt:
|
01/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
|
Title:
|
STRUCTURE FOR SYMMETRICAL CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
12013511
|
Filing Dt:
|
01/14/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
|
Title:
|
IMMERSION LITHOGRAPHIC PROCESS USING A VARIABLE SCAN SPEED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12014959
|
Filing Dt:
|
01/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
|
Title:
|
REMOVING MATERIAL FROM DEFECTIVE OPENING IN GLASS MOLD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12019240
|
Filing Dt:
|
01/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
|
Title:
|
SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12027675
|
Filing Dt:
|
02/07/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
|
Title:
|
METHOD FOR FABRICATION OF POLYCRYSTALLINE DIODES FOR RESISTIVE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12028895
|
Filing Dt:
|
02/11/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
|
Title:
|
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FORMATION OF AT LEAST ONE SIDEWALL SPACER STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
12032728
|
Filing Dt:
|
02/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
|
Title:
|
METHOD AND COMPUTER SYSTEM FOR OPTIMIZING THE SIGNAL TIME BEHAVIOR OF AN ELECTRONIC CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
12035462
|
Filing Dt:
|
02/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
|
Title:
|
TOPCOAT COMPOSITIONS AND METHODS OF USE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12046750
|
Filing Dt:
|
03/12/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/26/2009
| | | | |
|
Title:
|
DESIGN STRUCTURE FOR ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
12048461
|
Filing Dt:
|
03/14/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
|
Title:
|
ELETROSTATIC DISCHARGE (ESD) DEVICE AND METHOD OF FABRICATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
12049258
|
Filing Dt:
|
03/14/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
|
Title:
|
PATTERNED SILICON-ON-INSULATOR LAYERS AND METHODS FOR FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12055513
|
Filing Dt:
|
03/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
|
Title:
|
AROMATIC VINYL ETHER BASED REVERSE-TONE STEP AND FLASH IMPRINT LITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12055686
|
Filing Dt:
|
03/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
|
Title:
|
METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
12057565
|
Filing Dt:
|
03/28/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
|
Title:
|
METHODS FOR FORMING SURFACE FEATURES USING SELF-ASSEMBLING MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
12060889
|
Filing Dt:
|
04/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
|
Title:
|
ON-CHIP ELECTRICALLY ALTERABLE RESISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
12060922
|
Filing Dt:
|
04/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
|
Title:
|
SIMULTANEOUS CONDITIONING OF A PLURALITY OF MEMORY CELLS THROUGH SERIES RESISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12061283
|
Filing Dt:
|
04/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
|
Title:
|
MATERIALS HAVING PREDEFINED MORPHOLOGIES AND METHODS OF FORMATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2010
|
Application #:
|
12062972
|
Filing Dt:
|
04/04/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
|
Title:
|
LOW THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE WITH DUAL THRESHOLD VOLTAGE CONTROL MEANS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
12099175
|
Filing Dt:
|
04/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/08/2009
| | | | |
|
Title:
|
FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
12100592
|
Filing Dt:
|
04/10/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
|
Title:
|
DESIGN STRUCTURE FOR ELECTRICALLY TUNABLE RESISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
12102097
|
Filing Dt:
|
04/14/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/04/2010
| | | | |
|
Title:
|
HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
12103000
|
Filing Dt:
|
04/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
|
Title:
|
TRENCH WIDENING WITHOUT MERGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2012
|
Application #:
|
12103765
|
Filing Dt:
|
04/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12107573
|
Filing Dt:
|
04/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
|
Title:
|
MEMORY CELL HAVING A BURIED PHASE CHANGE REGION AND METHOD FOR FABRICATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12113510
|
Filing Dt:
|
05/01/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/05/2009
| | | | |
|
Title:
|
TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
12115065
|
Filing Dt:
|
05/05/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
|
Title:
|
HYBRID ORIENTATION SOI SUBSTRATES, AND METHOD FOR FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2012
|
Application #:
|
12120701
|
Filing Dt:
|
05/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
|
Title:
|
DESIGN STRUCTURES FOR SEMICONDUCTOR STRUCTURES WITH ERROR DETECTION AND CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12120899
|
Filing Dt:
|
05/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
|
Title:
|
THREE-DIMENSIONAL CASCADED POWER DISTRIBUTION IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
12130472
|
Filing Dt:
|
05/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR IMPROVING SRAM CELL STABILTY BY USING BOOSTED WORD LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
|
Application #:
|
12136163
|
Filing Dt:
|
06/10/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/25/2008
| | | | |
|
Title:
|
POSITIVE PHOTORESIST COMPOSITION WITH A POLYMER INCLUDING A FLUOROSULFONAMIDE GROUP AND PROCESS FOR ITS USE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
12137640
|
Filing Dt:
|
06/12/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2009
|
Application #:
|
12141121
|
Filing Dt:
|
06/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
SERVO SYSTEM FOR A TWO-DIMENSIONAL MICRO-ELECTROMECHANICAL SYSTEM (MEMS)-BASED SCANNER AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
12142239
|
Filing Dt:
|
06/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12163172
|
Filing Dt:
|
06/27/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
STRUCTURE TO FACILITATE PLATING INTO HIGH ASPECT RATIO VIAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
12166811
|
Filing Dt:
|
07/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
|
Title:
|
SYSTEM AND COMPUTER PROGRAM FOR VERIFYING PERFORMANCE OF AN ARRAY BY SIMULATING OPERATION OF EDGE CELLS IN A FULL ARRAY MODEL
|
|
