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Patent #:
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Issue Dt:
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02/19/2013
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Application #:
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12703211
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Filing Dt:
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02/10/2010
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Publication #:
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Pub Dt:
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08/11/2011
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Title:
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METHODS OF FORMING STRUCTURES WITH A FOCUSED ION BEAM FOR USE IN ATOMIC FORCE PROBING AND STRUCTURES FOR USE IN ATOMIC FORCE PROBING
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Patent #:
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Issue Dt:
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02/05/2013
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Application #:
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12707962
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Filing Dt:
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02/18/2010
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Publication #:
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Pub Dt:
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08/19/2010
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Title:
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POLARIZATION MONITORING RETICLE DESIGN FOR HIGH NUMERICAL APERTURE LITHOGRAPHY SYSTEMS
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Patent #:
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Issue Dt:
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11/11/2014
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Application #:
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12711322
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Filing Dt:
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02/24/2010
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Publication #:
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Pub Dt:
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09/02/2010
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Title:
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STRAIN ENGINEERING IN SEMICONDUCTOR DEVICES BY USING A PIEZOELECTRIC MATERIAL
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Patent #:
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Issue Dt:
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09/25/2012
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Application #:
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12718567
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Filing Dt:
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03/05/2010
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Publication #:
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Pub Dt:
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09/08/2011
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Title:
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SPATIAL CORRELATION-BASED ESTIMATION OF YIELD OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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12719058
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Filing Dt:
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03/08/2010
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Publication #:
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Pub Dt:
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09/08/2011
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Title:
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GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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12/10/2013
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Application #:
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12723842
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Filing Dt:
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03/15/2010
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Publication #:
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Pub Dt:
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09/15/2011
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Title:
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NANOPORE BASED DEVICE FOR CUTTING LONG DNA MOLECULES INTO FRAGMENTS
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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12731369
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Filing Dt:
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03/25/2010
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Publication #:
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Pub Dt:
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07/15/2010
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Title:
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New Flux Composition and Process For Use Thereof
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Patent #:
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Issue Dt:
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01/22/2013
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Application #:
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12731469
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Filing Dt:
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03/25/2010
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Publication #:
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Pub Dt:
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09/29/2011
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Title:
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TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS
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Patent #:
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Issue Dt:
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10/14/2014
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Application #:
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12749890
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Filing Dt:
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03/30/2010
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Publication #:
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Pub Dt:
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09/30/2010
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Title:
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ENHANCING ADHESION OF INTERLAYER DIELECTRIC MATERIALS OF SEMICONDUCTOR DEVICES BY SUPPRESSING SILICIDE FORMATION AT THE SUBSTRATE EDGE
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Patent #:
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Issue Dt:
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03/05/2013
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Application #:
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12753270
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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10/06/2011
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Title:
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CONTROLLING FERROELECTRICITY IN DIELECTRIC FILMS BY PROCESS INDUCED UNIAXIAL STRAIN
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Patent #:
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Issue Dt:
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05/07/2013
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Application #:
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12754917
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Filing Dt:
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04/06/2010
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Publication #:
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Pub Dt:
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10/06/2011
| | | | |
Title:
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FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION
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Patent #:
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Issue Dt:
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07/12/2011
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Application #:
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12759479
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Filing Dt:
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04/13/2010
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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PHASE CHANGE MEMORY WITH DUAL WORD LINES AND SOURCE LINES AND METHOD OF OPERATING SAME
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12764244
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Filing Dt:
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04/21/2010
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Publication #:
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Pub Dt:
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10/27/2011
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Title:
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SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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12765275
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Filing Dt:
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04/22/2010
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Publication #:
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Pub Dt:
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11/11/2010
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Title:
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ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS
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Patent #:
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Issue Dt:
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04/09/2013
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Application #:
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12766468
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Filing Dt:
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04/23/2010
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Publication #:
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Pub Dt:
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10/27/2011
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Title:
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USE OF EPITAXIAL NI SILICIDE
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Patent #:
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Issue Dt:
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08/21/2012
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Application #:
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12770420
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Filing Dt:
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04/29/2010
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Publication #:
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Pub Dt:
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11/03/2011
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Title:
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CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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12774223
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Filing Dt:
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05/20/2010
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Publication #:
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Pub Dt:
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11/24/2011
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Title:
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Enhanced Modularity in Heterogeneous 3D Stacks
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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12776674
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Filing Dt:
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05/10/2010
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Publication #:
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Pub Dt:
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11/18/2010
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Title:
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MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMATION IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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12776879
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Filing Dt:
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05/10/2010
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Publication #:
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Pub Dt:
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11/18/2010
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Title:
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SEMICONDUCTOR ELEMENT FORMED IN A CRYSTALLINE SUBSTRATE MATERIAL AND COMPRISING AN EMBEDDED IN SITU DOPED SEMICONDUCTOR MATERIAL
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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12778130
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Filing Dt:
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05/12/2010
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Publication #:
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Pub Dt:
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11/17/2011
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Title:
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CIRCUIT DEVICE WITH SIGNAL LINE TRANSITION ELEMENT
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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12779100
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Filing Dt:
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05/13/2010
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Publication #:
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Pub Dt:
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11/17/2011
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Title:
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METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS
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Patent #:
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Issue Dt:
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02/26/2013
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Application #:
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12780193
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Filing Dt:
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05/14/2010
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Publication #:
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Pub Dt:
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11/17/2011
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Title:
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NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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12787461
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Filing Dt:
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05/26/2010
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Publication #:
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Pub Dt:
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12/30/2010
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Title:
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UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING
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Patent #:
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Issue Dt:
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01/25/2011
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Application #:
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12788521
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Filing Dt:
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05/27/2010
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Publication #:
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Pub Dt:
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09/16/2010
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Title:
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SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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12793046
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Filing Dt:
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06/03/2010
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Publication #:
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Pub Dt:
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12/08/2011
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Title:
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CONTACT RESISTIVITY REDUCTION IN TRANSISTOR DEVICES BY DEEP LEVEL IMPURITY FORMATION
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Patent #:
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Issue Dt:
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02/12/2013
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Application #:
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12795962
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Filing Dt:
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06/08/2010
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Publication #:
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Pub Dt:
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12/08/2011
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Title:
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STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC
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Patent #:
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Issue Dt:
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04/23/2013
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Application #:
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12797420
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Filing Dt:
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06/09/2010
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Publication #:
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Pub Dt:
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12/15/2011
| | | | |
Title:
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SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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12817249
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Filing Dt:
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06/17/2010
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Publication #:
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Pub Dt:
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12/22/2011
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Title:
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TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE
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Patent #:
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Issue Dt:
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10/22/2013
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Application #:
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12818828
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Filing Dt:
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06/18/2010
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Publication #:
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Pub Dt:
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12/22/2011
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Title:
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INTERFACE-FREE METAL GATE STACK
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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12821507
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Filing Dt:
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06/23/2010
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Publication #:
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Pub Dt:
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12/29/2011
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Title:
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SHORT CHANNEL SEMICONDUCTOR DEVICES WITH REDUCED HALO DIFFUSION
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Patent #:
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Issue Dt:
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12/03/2013
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Application #:
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12822021
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Filing Dt:
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06/23/2010
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Publication #:
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Pub Dt:
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12/29/2011
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Title:
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PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT
|
|
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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12823660
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Filing Dt:
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06/25/2010
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Publication #:
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Pub Dt:
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12/30/2010
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Title:
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NON-INSULATING STRESSED MATERIAL LAYERS IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES
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|
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Patent #:
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|
Issue Dt:
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05/28/2013
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Application #:
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12823728
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Filing Dt:
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06/25/2010
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Publication #:
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Pub Dt:
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12/29/2011
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Title:
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FERRO-ELECTRIC CAPACITOR MODULES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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|
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Patent #:
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|
Issue Dt:
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11/19/2013
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Application #:
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12823984
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Filing Dt:
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06/25/2010
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Publication #:
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Pub Dt:
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12/29/2011
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Title:
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Digital Interface for Fast, Inline, Statistical Characterization of Process, MOS Device and Circuit Variations
|
|
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Patent #:
|
|
Issue Dt:
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07/23/2013
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Application #:
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12825791
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Filing Dt:
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06/29/2010
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Publication #:
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Pub Dt:
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12/29/2011
| | | | |
Title:
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FIELD EFFECT TRANSISTOR DEVICE
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|
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Patent #:
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Issue Dt:
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08/27/2013
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Application #:
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12832375
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Filing Dt:
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07/08/2010
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Publication #:
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Pub Dt:
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01/12/2012
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Title:
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METHOD TO EVALUATE EFFECTIVENESS OF SUBSTRATE CLEANNESS AND QUANTITY OF PIN HOLES IN AN ANTIREFLECTIVE COATING OF A SOLAR CELL
|
|
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Patent #:
|
|
Issue Dt:
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10/01/2013
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Application #:
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12835967
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Filing Dt:
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07/14/2010
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Publication #:
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Pub Dt:
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11/04/2010
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Title:
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INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING STRESSED LAYERS WITH AN INTERMEDIATE BUFFER MATERIAL
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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12838597
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Filing Dt:
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07/19/2010
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Publication #:
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Pub Dt:
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01/19/2012
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Title:
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TECHNIQUES FOR FORMING NARROW COPPER FILLED VIAS HAVING IMPROVED CONDUCTIVITY
|
|
|
Patent #:
|
|
Issue Dt:
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05/28/2013
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Application #:
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12839026
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Filing Dt:
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07/19/2010
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Publication #:
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Pub Dt:
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02/03/2011
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Title:
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METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM
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|
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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12839455
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Filing Dt:
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07/20/2010
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Publication #:
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Pub Dt:
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02/03/2011
| | | | |
Title:
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METHOD OF MANUFACTURING A CMOS DEVICE INCLUDING MOLECULAR STORAGE ELEMENTS IN A VIA LEVEL
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|
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Patent #:
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Issue Dt:
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04/30/2013
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Application #:
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12840689
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Filing Dt:
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07/21/2010
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Publication #:
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Pub Dt:
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01/26/2012
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Title:
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METHOD AND STRUCTURE FOR BALANCING POWER AND PERFORMANCE USING FLUORINE AND NITROGEN DOPED SUBSTRATES
|
|
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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12842548
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Filing Dt:
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07/23/2010
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Publication #:
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Pub Dt:
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02/03/2011
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Title:
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INCREASED DENSITY OF LOW-K DIELECTRIC MATERIALS IN SEMICONDUCTOR DEVICES BY APPLYING A UV TREATMENT
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|
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Patent #:
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Issue Dt:
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05/14/2013
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Application #:
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12844263
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Filing Dt:
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07/27/2010
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Publication #:
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Pub Dt:
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02/03/2011
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Title:
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THREE-DIMENSIONAL SEMICONDUCTOR DEVICE COMPRISING AN INTER-DIE CONNECTION ON THE BASIS OF FUNCTIONAL MOLECULES
|
|
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12849171
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Filing Dt:
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08/03/2010
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Publication #:
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Pub Dt:
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02/09/2012
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Title:
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FRACTURING CONTINUOUS PHOTOLITHOGRAPHY MASKS
|
|
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Patent #:
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Issue Dt:
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02/07/2012
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Application #:
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12851232
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Filing Dt:
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08/05/2010
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Publication #:
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Pub Dt:
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12/02/2010
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Title:
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VERTICAL FIELD EFFECT TRANSISTOR ARRAYS INCLUDING GATE ELECTRODES ANNULARLY SURROUNDING SEMICONDUCTOR PILLARS
|
|
|
Patent #:
|
|
Issue Dt:
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03/06/2012
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Application #:
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12853354
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Filing Dt:
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08/10/2010
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Publication #:
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Pub Dt:
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12/23/2010
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Title:
|
METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS USING A PROTECTIVE SIDEWALL SPACER
|
|
|
Patent #:
|
|
Issue Dt:
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08/27/2013
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Application #:
|
12854995
|
Filing Dt:
|
08/12/2010
|
Publication #:
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|
Pub Dt:
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03/03/2011
| | | | |
Title:
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UV IRRADIANCE MONITORING IN SEMICONDUCTOR PROCESSING USING A TEMPERATURE DEPENDENT SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
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Application #:
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12862203
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Filing Dt:
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08/24/2010
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Publication #:
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Pub Dt:
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03/03/2011
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Title:
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STRESS ADJUSTMENT IN STRESSED DIELECTRIC MATERIALS OF SEMICONDUCTOR DEVICES BY STRESS RELAXATION BASED ON RADIATION
|
|
|
Patent #:
|
|
Issue Dt:
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03/04/2014
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Application #:
|
12869973
|
Filing Dt:
|
08/27/2010
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Publication #:
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Pub Dt:
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03/01/2012
| | | | |
Title:
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CONTROLLING NON-PROCESS OF RECORD (POR) PROCESS LIMITING YIELD (PLY) INSPECTION WORK
|
|
|
Patent #:
|
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Issue Dt:
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11/05/2013
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Application #:
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12873058
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Filing Dt:
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08/31/2010
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Publication #:
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Pub Dt:
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03/01/2012
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Title:
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POST-FABRICATION SELF-ALIGNED INITIALIZATION OF INTEGRATED DEVICES
|
|
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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12876518
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Filing Dt:
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09/07/2010
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Publication #:
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Pub Dt:
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12/30/2010
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Title:
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SOLUTION FOR FORMING POLISHING SLURRY, POLISHING SLURRY AND RELATED METHODS
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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12878297
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Filing Dt:
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09/09/2010
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Publication #:
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Pub Dt:
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03/15/2012
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Title:
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Implementing Interleaved-Dielectric Joining of Multi-Layer Laminates
|
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Patent #:
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Issue Dt:
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02/18/2014
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Application #:
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12880085
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Filing Dt:
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09/11/2010
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Publication #:
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Pub Dt:
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03/15/2012
| | | | |
Title:
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Transistor having replacement metal gate and process for fabricating the same
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Patent #:
|
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Issue Dt:
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07/23/2013
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Application #:
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12885665
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Filing Dt:
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09/20/2010
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Publication #:
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Pub Dt:
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03/22/2012
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Title:
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STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
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07/09/2013
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Application #:
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12888828
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Filing Dt:
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09/23/2010
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Publication #:
|
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Pub Dt:
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03/29/2012
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Title:
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ASYMMETRIC WEDGE JFET, RELATED METHOD AND DESIGN STRUCTURE
|
|
|
Patent #:
|
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Issue Dt:
|
05/13/2014
|
Application #:
|
12890051
|
Filing Dt:
|
09/24/2010
|
Publication #:
|
|
Pub Dt:
|
03/29/2012
| | | | |
Title:
|
STRUCTURES AND TECHNIQUES FOR ATOMIC LAYER DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
12891403
|
Filing Dt:
|
09/27/2010
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY CORNER ROUNDING BASED ON A SACRIFICIAL FILL MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
12894469
|
Filing Dt:
|
09/30/2010
|
Publication #:
|
|
Pub Dt:
|
05/05/2011
| | | | |
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE COMPRISING REPLACEMENT GATE ELECTRODE STRUCTURES WITH AN ENHANCED DIFFUSION BARRIER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
12897230
|
Filing Dt:
|
10/04/2010
|
Publication #:
|
|
Pub Dt:
|
04/05/2012
| | | | |
Title:
|
ISOLATION STRUCTURES FOR GLOBAL SHUTTER IMAGER PIXEL, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2012
|
Application #:
|
12899333
|
Filing Dt:
|
10/06/2010
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED ON THE BASIS OF A SIMPLIFIED SPACER REGIME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12899638
|
Filing Dt:
|
10/07/2010
|
Publication #:
|
|
Pub Dt:
|
04/12/2012
| | | | |
Title:
|
TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
12901079
|
Filing Dt:
|
10/08/2010
|
Publication #:
|
|
Pub Dt:
|
01/27/2011
| | | | |
Title:
|
HEATER AND MEMORY CELL, MEMORY DEVICE AND RECORDING HEAD INCLUDING THE HEATER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
12905711
|
Filing Dt:
|
10/15/2010
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
PREDOPED SEMICONDUCTOR MATERIAL FOR A HIGH-K METAL GATE ELECTRODE STRUCTURE OF P- AND N-CHANNEL TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
12906707
|
Filing Dt:
|
10/18/2010
|
Publication #:
|
|
Pub Dt:
|
04/19/2012
| | | | |
Title:
|
METHODOLOGY ON DEVELOPING METAL FILL AS LIBRARY DEVICE AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
12907186
|
Filing Dt:
|
10/19/2010
|
Publication #:
|
|
Pub Dt:
|
02/10/2011
| | | | |
Title:
|
SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
12907596
|
Filing Dt:
|
10/19/2010
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
ENHANCED CONFINEMENT OF SENSITIVE MATERIALS OF A HIGH-K METAL GATE ELECTRODE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12914123
|
Filing Dt:
|
10/28/2010
|
Publication #:
|
|
Pub Dt:
|
08/04/2011
| | | | |
Title:
|
SEMICONDUCTOR ELEMENT COMPRISING A LOW VARIATION SUBSTRATE DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
12915168
|
Filing Dt:
|
10/29/2010
|
Publication #:
|
|
Pub Dt:
|
08/04/2011
| | | | |
Title:
|
SOI SEMICONDUCTOR DEVICE COMPRISING SUBSTRATE DIODES HAVING A TOPOGRAPHY TOLERANT CONTACT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
12939462
|
Filing Dt:
|
11/04/2010
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
ASYMMETRIC HETERO-STRUCTURE FET AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2017
|
Application #:
|
12942011
|
Filing Dt:
|
11/08/2010
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
OPTIMIZING STORAGE CLOUD ENVIRONMENTS THROUGH ADAPTIVE STATISTICAL MODELING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
12943084
|
Filing Dt:
|
11/10/2010
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
12943987
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
CREATING ANISOTROPICALLY DIFFUSED JUNCTIONS IN FIELD EFFECT TRANSISTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
12946915
|
Filing Dt:
|
11/16/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12948092
|
Filing Dt:
|
11/17/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
12949148
|
Filing Dt:
|
11/18/2010
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A CUT-WAY HOLE TO EXPOSE A PORTION OF A HARDMASK LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
12949888
|
Filing Dt:
|
11/19/2010
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
SOURCE/DRAIN-TO-SOURCE/DRAIN RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2015
|
Application #:
|
12955388
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
12956291
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
BODY CONTROLLED DOUBLE CHANNEL TRANSISTOR AND CIRCUITS COMPRISING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
12958678
|
Filing Dt:
|
12/02/2010
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
MECHANICAL FIXTURE OF PELLICLE TO LITHOGRAPHIC PHOTOMASK
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
12959824
|
Filing Dt:
|
12/03/2010
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
12962968
|
Filing Dt:
|
12/08/2010
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
CONTACT ELEMENTS OF A SEMICONDUCTOR DEVICE FORMED BY ELECTROLESS PLATING AND EXCESS MATERIAL REMOVAL WITH REDUCED SHEER FORCES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
12963054
|
Filing Dt:
|
12/08/2010
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING ASYMMETRIC LIGHTLY DOPED DRAIN (LDD) REGION, RELATED METHOD AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
12963134
|
Filing Dt:
|
12/08/2010
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
REDUCTION OF MECHANICAL STRESS IN METAL STACKS OF SOPHISTICATED SEMICONDUCTOR DEVICES DURING DIE-SUBSTRATE SOLDERING BY AN ENHANCED COOL DOWN REGIME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12963139
|
Filing Dt:
|
12/08/2010
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
SOLDER BUMP CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
12964136
|
Filing Dt:
|
12/09/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
REDUCED STI TOPOGRAPHY IN HIGH-K METAL GATE TRANSISTORS BY USING A MASK AFTER CHANNEL SEMICONDUCTOR ALLOY DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
12964359
|
Filing Dt:
|
12/09/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
CHIP PACKAGE INCLUDING MULTIPLE SECTIONS FOR REDUCING CHIP PACKAGE INTERACTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2013
|
Application #:
|
12964448
|
Filing Dt:
|
12/09/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
STRESS REDUCTION IN CHIP PACKAGING BY A STRESS COMPENSATION REGION FORMED AROUND THE CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
12966302
|
Filing Dt:
|
12/13/2010
|
Publication #:
|
|
Pub Dt:
|
01/05/2012
| | | | |
Title:
|
Semiconductor Device Including Ultra Low-K (ULK) Metallization Stacks with Reduced Chip-Package Interaction
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12967268
|
Filing Dt:
|
12/14/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2014
|
Application #:
|
12967329
|
Filing Dt:
|
12/14/2010
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
PARTIALLY DEPLETED (PD) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (VT) LOWERING AND METHOD OF FORMING THE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
12967625
|
Filing Dt:
|
12/14/2010
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
METHOD OF FABRICATING PHOTOCONDUCTOR-ON-ACTIVE PIXEL DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
12969969
|
Filing Dt:
|
12/16/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
PLANARIZATION OF A MATERIAL SYSTEM IN A SEMICONDUCTOR DEVICE BY USING A NON-SELECTIVE IN SITU PREPARED SLURRY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12973377
|
Filing Dt:
|
12/20/2010
|
Publication #:
|
|
Pub Dt:
|
04/14/2011
| | | | |
Title:
|
BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12977134
|
Filing Dt:
|
12/23/2010
|
Publication #:
|
|
Pub Dt:
|
04/21/2011
| | | | |
Title:
|
ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
12983352
|
Filing Dt:
|
01/03/2011
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING BODY CONNECTED FETS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12983377
|
Filing Dt:
|
01/03/2011
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
METHOD FOR DIRECT HEAT SINK ATTACHMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
12983477
|
Filing Dt:
|
01/03/2011
|
Publication #:
|
|
Pub Dt:
|
05/12/2011
| | | | |
Title:
|
METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13006148
|
Filing Dt:
|
01/13/2011
|
Publication #:
|
|
Pub Dt:
|
01/05/2012
| | | | |
Title:
|
TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET AND SUPERIOR UNIFORMITY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13006522
|
Filing Dt:
|
01/14/2011
|
Publication #:
|
|
Pub Dt:
|
01/05/2012
| | | | |
Title:
|
METHOD AND SYSTEM FOR EXCURSION MONITORING IN OPTICAL LITHOGRAPHY PROCESSES IN MICRO DEVICE FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13008935
|
Filing Dt:
|
01/19/2011
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
MINIMIZING THE MAXIMUM REQUIRED LINK CAPACITY FOR THREE-DIMENSIONAL INTERCONNECT ROUTING
|
|