Total properties:
730
Page
6
of
8
Pages:
1 2 3 4 5 6 7 8
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13489244
|
Filing Dt:
|
06/05/2012
|
|
Title:
|
AQUA REGIA AND HYDROGEN PEROXIDE HCL COMBINATION TO REMOVE NI AND NIPT RESIDUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13490840
|
Filing Dt:
|
06/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUITS HAVING A CONTINUOUS ACTIVE AREA AND METHODS FOR FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
13529264
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2013
| | | | |
|
Title:
|
OVERHEAD SUBSTRATE HANDLING AND STORAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13529898
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2013
| | | | |
|
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH DRIFT REGIONS AND REPLACEMENT GATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13533182
|
Filing Dt:
|
06/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
|
Title:
|
FORMATION OF ALPHA PARTICLE SHIELDS IN CHIP PACKAGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13534462
|
Filing Dt:
|
06/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
|
Title:
|
SEMICONDUCTOR SWITCHING DEVICE EMPLOYING A QUANTUM DOT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13535466
|
Filing Dt:
|
06/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
|
Title:
|
SPIN-ON FORMULATION AND METHOD FOR STRIPPING AN ION IMPLANTED PHOTORESIST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13535528
|
Filing Dt:
|
06/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
|
Title:
|
SPIN-ON FORMULATION AND METHOD FOR STRIPPING AN ION IMPLANTED PHOTORESIST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2016
|
Application #:
|
13535675
|
Filing Dt:
|
06/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
|
Title:
|
ENHANCED MODULARITY IN HETEROGENEOUS 3D STACKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
13535694
|
Filing Dt:
|
06/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
|
Title:
|
Enhanced Modularity in Heterogeneous 3D Stacks
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13536366
|
Filing Dt:
|
06/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
|
Title:
|
METHOD OF FORMING SWITCHING DEVICE HAVING A MOLYBDENUM OXYNITRIDE METAL GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13539700
|
Filing Dt:
|
07/02/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
|
Title:
|
METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SIGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13554294
|
Filing Dt:
|
07/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13557385
|
Filing Dt:
|
07/25/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
CONTROLLING FERROELECTRICITY IN DIELECTRIC FILMS BY PROCESS INDUCED UNIAXIAL STRAIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13557501
|
Filing Dt:
|
07/25/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13559182
|
Filing Dt:
|
07/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
METHOD FOR FABRICATING TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13560012
|
Filing Dt:
|
07/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2014
| | | | |
|
Title:
|
RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF FORMING IMPLANT MASKING LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13560340
|
Filing Dt:
|
07/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
CMOS WITH CHANNEL P-FINFET AND CHANNEL N-FINFET HAVING DIFFERENT CRYSTALLINE ORIENTATIONS AND PARALLEL FINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13564812
|
Filing Dt:
|
08/02/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
AROMATIC VINYL ETHER BASED REVERSE-TONE STEP AND FLASH IMPRINT LITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13565294
|
Filing Dt:
|
08/02/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13566050
|
Filing Dt:
|
08/03/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
SELF ALIGNED CARBIDE SOURCE/DRAIN FET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13568670
|
Filing Dt:
|
08/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13568689
|
Filing Dt:
|
08/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
13568839
|
Filing Dt:
|
08/07/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13569741
|
Filing Dt:
|
08/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
FET WITH FUSI GATE AND REDUCED SOURCE/DRAIN CONTACT RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13570470
|
Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
NANOPORE BASED DEVICE FOR CUTTING LONG DNA MOLECULES INTO FRAGMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13570692
|
Filing Dt:
|
08/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
PIEZOELECTRIC BASED ENERGY SUPPLY USING INDEPENDENT PIEZOELECTRIC COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13572742
|
Filing Dt:
|
08/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
BEOL COMPATIBLE FET STRUCTRURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13584981
|
Filing Dt:
|
08/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY PERFORMING A DRY CHEMICAL REMOVAL PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13590300
|
Filing Dt:
|
08/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
SPATIAL CORRELATION-BASED ESTIMATION OF YIELD OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13595025
|
Filing Dt:
|
08/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
|
Title:
|
IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13596410
|
Filing Dt:
|
08/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2015
|
Application #:
|
13603008
|
Filing Dt:
|
09/04/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13604230
|
Filing Dt:
|
09/05/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
METHOD TO EVALUATE EFFECTIVENESS OF SUBSTRATE CLEANNESS AND QUANTITY OF PIN HOLES IN AN ANTIREFLECTIVE COATING OF A SOLAR CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13605136
|
Filing Dt:
|
09/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
FORMATION OF DIVIDERS BETWEEN GATE ENDS OF FIELD EFFECT TRANSISTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13607674
|
Filing Dt:
|
09/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
|
TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13608409
|
Filing Dt:
|
09/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
|
Near-Infrared Absorbing Film Compositions
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13610263
|
Filing Dt:
|
09/11/2012
|
|
Title:
|
METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY PERFORMING A DEPOSITION-ETCH-DEPOSITION SEQUENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13611423
|
Filing Dt:
|
09/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
|
PIXEL SENSORS OF MULTIPLE PIXEL SIZE AND METHODS OF IMPLANT DOSE CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13612159
|
Filing Dt:
|
09/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
|
MULTILAYERED LOW K CAP WITH CONFORMAL GAP FILL AND UV STABLE COMPRESSIVE STRESS PROPERTIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13612240
|
Filing Dt:
|
09/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/10/2013
| | | | |
|
Title:
|
METHOD OF FABRICATING AN EPITAXIAL NI SILICIDE FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13614930
|
Filing Dt:
|
09/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
|
Title:
|
ROBUST SPECTRAL ANALYZER FOR ONE-DIMENSIONAL AND MULTI-DIMENSIONAL DATA ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13621242
|
Filing Dt:
|
09/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
|
Title:
|
METHOD FOR MAKING HIGH-SPEED CERAMIC MODULES WITH HYBRID REFERENCING SCHEME FOR IMPROVED PERFORMANCE AND REDUCED COST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13658148
|
Filing Dt:
|
10/23/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
|
Title:
|
CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13658861
|
Filing Dt:
|
10/24/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/21/2013
| | | | |
|
Title:
|
SERIAL IRRADIATION OF A SUBSTRATE BY MULTIPLE RADIATION SOURCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13659236
|
Filing Dt:
|
10/24/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
|
Title:
|
Polarization Monitoring Reticle Design for High Numerical Aperture Lithography Systems
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13663836
|
Filing Dt:
|
10/30/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
|
Title:
|
METHODS OF FORMING STRUCTURES WITH A FOCUSED ION BEAM FOR USE IN ATOMIC FORCE PROBING AND STRUCTURES FOR USE IN ATOMIC FORCE PROBING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13671186
|
Filing Dt:
|
11/07/2012
|
|
Title:
|
SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13675442
|
Filing Dt:
|
11/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
|
Title:
|
PROTECTIVE TREATMENT FOR POROUS MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13676174
|
Filing Dt:
|
11/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13682771
|
Filing Dt:
|
11/21/2012
|
|
Title:
|
USE OF POLARIZATION AND COMPOSITE ILLUMINATION SOURCE FOR ADVANCED OPTICAL LITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2017
|
Application #:
|
13716693
|
Filing Dt:
|
12/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
|
Title:
|
METAL CAPACITOR DESIGN FOR IMPROVED RELIABILITY AND GOOD ELECTRICAL CONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13735470
|
Filing Dt:
|
01/07/2013
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
|
Title:
|
RETICLE CARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13736505
|
Filing Dt:
|
01/08/2013
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
|
Title:
|
NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13737611
|
Filing Dt:
|
01/09/2013
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
|
Title:
|
THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13740343
|
Filing Dt:
|
01/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
SELECTIVE REMOVAL OF GATE STRUCTURE SIDEWALL(S) TO FACILITATE SIDEWALL SPACER PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13748038
|
Filing Dt:
|
01/23/2013
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
|
Title:
|
HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13749744
|
Filing Dt:
|
01/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
|
Title:
|
CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13749745
|
Filing Dt:
|
01/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
|
Title:
|
CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13752567
|
Filing Dt:
|
01/29/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
|
Title:
|
STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13756689
|
Filing Dt:
|
02/01/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
|
Title:
|
DOUBLE-PATTERN GATE FORMATION PROCESSING WITH CRITICAL DIMENSION CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13758386
|
Filing Dt:
|
02/04/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
|
Title:
|
SOLDER BUMP CONNECTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13759146
|
Filing Dt:
|
02/05/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13761610
|
Filing Dt:
|
02/07/2013
|
|
Title:
|
METHODS OF FORMING ISOLATION REGIONS FOR FINFET SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13762445
|
Filing Dt:
|
02/08/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
13765105
|
Filing Dt:
|
02/12/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
DEEP TRENCH DECOUPLING CAPACITOR AND METHODS OF FORMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13765797
|
Filing Dt:
|
02/13/2013
|
|
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13766922
|
Filing Dt:
|
02/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/14/2014
| | | | |
|
Title:
|
METHODS OF FORMING MULTIPLE N-TYPE SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES ON A SEMICONDUCTOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13766952
|
Filing Dt:
|
02/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
|
Title:
|
ISOLATION STRUCTURES FOR GLOBAL SHUTTER IMAGER PIXEL, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13770287
|
Filing Dt:
|
02/19/2013
|
|
Title:
|
CORRECTING FOR OVEREXPOSURE DUE TO OVERLAPPING EXPOSURES IN LITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13771294
|
Filing Dt:
|
02/20/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
|
Title:
|
METHODS OF INDUCING A DESIRED STRESS IN THE CHANNEL REGION OF A TRANSISTOR BY PERFORMING ION IMPLANTATION/ANNEAL PROCESSES ON THE GATE ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13771478
|
Filing Dt:
|
02/20/2013
|
|
Title:
|
EUV MASK DEFECT RECONSTRUCTION AND COMPENSATION REPAIR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13772402
|
Filing Dt:
|
02/21/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
|
Title:
|
SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13772993
|
Filing Dt:
|
02/21/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
|
Title:
|
DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13775369
|
Filing Dt:
|
02/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
|
Title:
|
FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13775570
|
Filing Dt:
|
02/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
|
Title:
|
METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13776911
|
Filing Dt:
|
02/26/2013
|
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
|
Title:
|
SOURCE/DRAIN-TO-SOURCE/DRAIN RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2016
|
Application #:
|
13778419
|
Filing Dt:
|
02/27/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
|
Title:
|
STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13783526
|
Filing Dt:
|
03/04/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
|
Title:
|
FIELD EFFECT TRANSISTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13783715
|
Filing Dt:
|
03/04/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
|
Title:
|
METHODS OF FORMING STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
13796674
|
Filing Dt:
|
03/12/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
13833139
|
Filing Dt:
|
03/15/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
|
Title:
|
POST-FABRICATION SELF-ALIGNED INITIALIZATION OF INTEGRATED DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13833735
|
Filing Dt:
|
03/15/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
|
Title:
|
DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13838956
|
Filing Dt:
|
03/15/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
|
Title:
|
HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13839020
|
Filing Dt:
|
03/15/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
|
Title:
|
HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13840790
|
Filing Dt:
|
03/15/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
|
Title:
|
METHODS FOR FABRICATING EUV MASKS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SUCH EUV MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13846229
|
Filing Dt:
|
03/18/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
|
Title:
|
SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13852043
|
Filing Dt:
|
03/28/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
|
Title:
|
METHODS OF FORMING MASKING LAYERS FOR USE IN FORMING INTEGRATED CIRCUIT PRODUCTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13858198
|
Filing Dt:
|
04/08/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
|
Title:
|
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE COMPRISING AN INTER-DIE CONNECTION ON THE BASIS OF FUNCTIONAL MOLECULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2015
|
Application #:
|
13865795
|
Filing Dt:
|
04/18/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2014
| | | | |
|
Title:
|
SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13866077
|
Filing Dt:
|
04/19/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2014
| | | | |
|
Title:
|
DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13866162
|
Filing Dt:
|
04/19/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
|
Title:
|
STRUCTURE FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13869662
|
Filing Dt:
|
04/24/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
|
Title:
|
ALIGNMENT CORRECTION SYSTEM AND METHOD OF USE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
13870411
|
Filing Dt:
|
04/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2016
|
Application #:
|
13874200
|
Filing Dt:
|
04/30/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2014
| | | | |
|
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH POLYCRYSTALLINE SILICON RESISTOR STRUCTURES USING A REPLACMENT GATE PROCESS FLOW, AND THE INTEGRATED CIRCUITS FABRICATED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13904060
|
Filing Dt:
|
05/29/2013
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
|
Title:
|
Self-Aligned Gate Electrode Diffusion Barriers
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13905271
|
Filing Dt:
|
05/30/2013
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
|
Title:
|
METHODS OF FORMING CONDUCTIVE STRUCTURES USING A SACRIFICIAL MATERIAL DURING A METAL HARD MASK REMOVAL PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
13905556
|
Filing Dt:
|
05/30/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
|
Title:
|
MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13907237
|
Filing Dt:
|
05/31/2013
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
|
Title:
|
METHOD FOR THE FORMATION OF A PROTECTIVE DUAL LINER FOR A SHALLOW TRENCH ISOLATION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13907690
|
Filing Dt:
|
05/31/2013
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
|
Title:
|
PREVENTION OF FACETING IN EPITAXIAL SOURCE DRAIN TRANSISTORS
|
|
