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Reel/Frame:048719/0864   Pages: 5
Recorded: 03/27/2019
Attorney Dkt #:LANGER ME
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 13
1
Patent #:
Issue Dt:
12/15/2020
Application #:
15944160
Filing Dt:
04/03/2018
Publication #:
Pub Dt:
10/03/2019
Title:
DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
2
Patent #:
Issue Dt:
07/05/2022
Application #:
15944179
Filing Dt:
04/03/2018
Title:
COMMUNICATING BETWEEN DATA PROCESSING ENGINES USING SHARED MEMORY
3
Patent #:
Issue Dt:
11/03/2020
Application #:
15944295
Filing Dt:
04/03/2018
Title:
DEVICE WITH DATA PROCESSING ENGINE ARRAY THAT ENABLES PARTIAL RECONFIGURATION
4
Patent #:
Issue Dt:
03/03/2020
Application #:
15944303
Filing Dt:
04/03/2018
Title:
STALL LOGIC FOR A DATA PROCESSING ENGINE IN AN INTEGRATED CIRCUIT
5
Patent #:
Issue Dt:
08/18/2020
Application #:
15944307
Filing Dt:
04/03/2018
Publication #:
Pub Dt:
10/03/2019
Title:
DEVICE WITH DATA PROCESSING ENGINE ARRAY
6
Patent #:
Issue Dt:
08/18/2020
Application #:
15944315
Filing Dt:
04/03/2018
Title:
CORE FOR A DATA PROCESSING ENGINE IN AN INTEGRATED CIRCUIT
7
Patent #:
Issue Dt:
07/13/2021
Application #:
15944393
Filing Dt:
04/03/2018
Title:
DATA SELECTION NETWORK FOR A DATA PROCESSING ENGINE IN AN INTEGRATED CIRCUIT
8
Patent #:
Issue Dt:
06/28/2022
Application #:
15944408
Filing Dt:
04/03/2018
Publication #:
Pub Dt:
10/03/2019
Title:
DATA PROCESSING ENGINE TILE ARCHITECTURE FOR AN INTEGRATED CIRCUIT
9
Patent #:
Issue Dt:
04/27/2021
Application #:
15944464
Filing Dt:
04/03/2018
Title:
STREAMING INTERCONNECT ARCHITECTURE FOR DATA PROCESSING ENGINE ARRAY
10
Patent #:
Issue Dt:
09/07/2021
Application #:
15944490
Filing Dt:
04/03/2018
Title:
DUAL MODE INTERCONNECT
11
Patent #:
Issue Dt:
05/25/2021
Application #:
15944578
Filing Dt:
04/03/2018
Title:
CASCADE STREAMING BETWEEN DATA PROCESSING ENGINES IN AN ARRAY
12
Patent #:
Issue Dt:
01/31/2023
Application #:
15944602
Filing Dt:
04/03/2018
Title:
EVENT-BASED DEBUG, TRACE, AND PROFILE IN DEVICE WITH DATA PROCESSING ENGINE ARRAY
13
Patent #:
Issue Dt:
04/28/2020
Application #:
15944617
Filing Dt:
04/03/2018
Publication #:
Pub Dt:
10/03/2019
Title:
SYSTEM-ON-CHIP INTERFACE ARCHITECTURE
Assignor
1
Exec Dt:
03/27/2019
Assignee
1
2100 LOGIC DRIVE
LEGAL DEPT.
SAN JOSE, CALIFORNIA 95124
Correspondence name and address
XILINX, INC.
2100 LOGIC DRIVE
LEGAL DEPT.
SAN JOSE, CA 95124

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