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Reel/Frame:022542/0876   Pages: 9
Recorded: 04/15/2009
Attorney Dkt #:CHANGE OF ADDRESS
Conveyance: CHANGE OF ADDRESS OF ASSIGNEE
Total properties: 228
Page 2 of 3
Pages: 1 2 3
1
Patent #:
6744688
Issue Dt:
06/01/2004
Application #:
10357394
Filing Dt:
02/04/2003
Publication #:
US20030161209
Pub Dt:
08/28/2003
Title:
SEARCHLINE CONTROL CIRCUIT AND POWER REDUCTION METHOD
2
Patent #:
6853231
Issue Dt:
02/08/2005
Application #:
10402130
Filing Dt:
03/31/2003
Publication #:
US20040189372
Pub Dt:
09/30/2004
Title:
TIMING VERNIER USING A DELAY LOCKED LOOP
3
Patent #:
6992972
Issue Dt:
01/31/2006
Application #:
10410375
Filing Dt:
04/09/2003
Publication #:
US20030189894
Pub Dt:
10/09/2003
Title:
FREQUENCY DIVISION MULTIPLEXING SYSTEM WITH SELECTABLE RATE
4
Patent #:
7353330
Issue Dt:
04/01/2008
Application #:
10425957
Filing Dt:
04/30/2003
Publication #:
US20040165608
Pub Dt:
08/26/2004
Title:
METHOD AND APPARATUS FOR PERFORMING REPEATED CONTENT ADDRESSABLE MEMORY SEARCHES
5
Patent #:
7062601
Issue Dt:
06/13/2006
Application #:
10430378
Filing Dt:
05/07/2003
Publication #:
US20040001380
Pub Dt:
01/01/2004
Title:
METHOD AND APPARATUS FOR INTERCONNECTING CONTENT ADDRESSABLE MEMORY DEVICES
6
Patent #:
6892279
Issue Dt:
05/10/2005
Application #:
10444600
Filing Dt:
05/27/2003
Publication #:
US20030200408
Pub Dt:
10/23/2003
Title:
METHOD AND APPARATUS FOR ACCELERATING RETRIEVAL OF DATA FROM A MEMORY SYSTEM WITH CACHE BY REDUCING LATENCY
7
Patent #:
6980448
Issue Dt:
12/27/2005
Application #:
10463218
Filing Dt:
06/17/2003
Publication #:
US20040036456
Pub Dt:
02/26/2004
Title:
BOOSTED VOLTAGE SUPPLY
8
Patent #:
6847573
Issue Dt:
01/25/2005
Application #:
10608719
Filing Dt:
06/26/2003
Publication #:
US20040017714
Pub Dt:
01/29/2004
Title:
SYNCHRONOUS SRAM-COMPATIBLE MEMORY AND METHOD OF DRIVING THE SAME
9
Patent #:
6822920
Issue Dt:
11/23/2004
Application #:
10639922
Filing Dt:
08/12/2003
Publication #:
US20040042327
Pub Dt:
03/04/2004
Title:
SRAM-COMPATIBLE MEMORY DEVICE EMPLOYING DRAM CELLS
10
Patent #:
7477716
Issue Dt:
01/13/2009
Application #:
10647664
Filing Dt:
08/25/2003
Publication #:
US20040264621
Pub Dt:
12/30/2004
Title:
START UP CIRCUIT FOR DELAY LOCKED LOOP
11
Patent #:
7266747
Issue Dt:
09/04/2007
Application #:
10694761
Filing Dt:
10/29/2003
Publication #:
US20040117723
Pub Dt:
06/17/2004
Title:
ERROR CORRECTION SCHEME FOR MEMORY
12
Patent #:
7006368
Issue Dt:
02/28/2006
Application #:
10702489
Filing Dt:
11/07/2003
Publication #:
US20040145934
Pub Dt:
07/29/2004
Title:
MISMATCH-DEPENDENT POWER ALLOCATION TECHNIQUE FOR MATCH-LINE SENSING IN CONTENT-ADDRESSABLE MEMORIES
13
Patent #:
7188211
Issue Dt:
03/06/2007
Application #:
10724576
Filing Dt:
12/01/2003
Publication #:
US20050001744
Pub Dt:
01/06/2005
Title:
BLOCK PROGRAMMABLE PRIORITY ENCODER IN A CAM
14
Patent #:
6891772
Issue Dt:
05/10/2005
Application #:
10804182
Filing Dt:
03/19/2004
Publication #:
US20040202036
Pub Dt:
10/14/2004
Title:
HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY
15
Patent #:
NONE
Issue Dt:
Application #:
10809421
Filing Dt:
03/26/2004
Publication #:
US20050213359
Pub Dt:
09/29/2005
Title:
Hybrid content addressable memory
16
Patent #:
7178001
Issue Dt:
02/13/2007
Application #:
10855968
Filing Dt:
05/28/2004
Publication #:
US20050033899
Pub Dt:
02/10/2005
Title:
SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
17
Patent #:
7120040
Issue Dt:
10/10/2006
Application #:
10856783
Filing Dt:
06/01/2004
Publication #:
US20050276086
Pub Dt:
12/15/2005
Title:
TERNARY CAM CELL FOR REDUCED MATCHLINE CAPACITANCE
18
Patent #:
7299330
Issue Dt:
11/20/2007
Application #:
10919491
Filing Dt:
08/17/2004
Publication #:
US20050081012
Pub Dt:
04/14/2005
Title:
HIGH BANDWIDTH MEMORY INTERFACE
19
Patent #:
7042771
Issue Dt:
05/09/2006
Application #:
10946016
Filing Dt:
09/22/2004
Publication #:
US20050036386
Pub Dt:
02/17/2005
Title:
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS
20
Patent #:
7279956
Issue Dt:
10/09/2007
Application #:
10996739
Filing Dt:
11/24/2004
Publication #:
US20060006929
Pub Dt:
01/12/2006
Title:
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
21
Patent #:
7176733
Issue Dt:
02/13/2007
Application #:
11009534
Filing Dt:
12/10/2004
Publication #:
US20050162200
Pub Dt:
07/28/2005
Title:
HIGH OUTPUT IMPEDANCE CHARGE PUMP FOR PLL/DLL
22
Patent #:
7038517
Issue Dt:
05/02/2006
Application #:
11037365
Filing Dt:
01/19/2005
Publication #:
US20050122144
Pub Dt:
06/09/2005
Title:
TIMING VERNIER USING A DELAY LOCKED LOOP
23
Patent #:
7227383
Issue Dt:
06/05/2007
Application #:
11041687
Filing Dt:
01/20/2005
Publication #:
US20050184758
Pub Dt:
08/25/2005
Title:
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
24
Patent #:
7190201
Issue Dt:
03/13/2007
Application #:
11050644
Filing Dt:
02/03/2005
Publication #:
US20060170471
Pub Dt:
08/03/2006
Title:
METHOD AND APPARATUS FOR INITIALIZING A DELAY LOCKED LOOP
25
Patent #:
7012850
Issue Dt:
03/14/2006
Application #:
11101413
Filing Dt:
04/08/2005
Publication #:
US20050180246
Pub Dt:
08/18/2005
Title:
HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY
26
Patent #:
7318123
Issue Dt:
01/08/2008
Application #:
11107958
Filing Dt:
04/18/2005
Publication #:
US20050246497
Pub Dt:
11/03/2005
Title:
METHOD AND APPARATUS FOR ACCELERATING RETRIEVAL OF DATA FROM A MEMORY SYSTEM WITH CACHE BY REDUCING LATENCY
27
Patent #:
8111607
Issue Dt:
02/07/2012
Application #:
11156140
Filing Dt:
06/17/2005
Publication #:
US20050232134
Pub Dt:
10/20/2005
Title:
FREQUENCY DIVISION MULTIPLEXING SYSTEM WITH SELECTABLE RATE
28
Patent #:
7248531
Issue Dt:
07/24/2007
Application #:
11195641
Filing Dt:
08/03/2005
Publication #:
US20070030749
Pub Dt:
02/08/2007
Title:
VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY
29
Patent #:
7129760
Issue Dt:
10/31/2006
Application #:
11205082
Filing Dt:
08/17/2005
Publication #:
US20060017484
Pub Dt:
01/26/2006
Title:
TIMING VERNIER USING A DELAY LOCKED LOOP
30
Patent #:
7602222
Issue Dt:
10/13/2009
Application #:
11238973
Filing Dt:
09/30/2005
Publication #:
US20070079147
Pub Dt:
04/05/2007
Title:
POWER UP CIRCUIT WITH LOW POWER SLEEP MODE OPERATION
31
Patent #:
7292061
Issue Dt:
11/06/2007
Application #:
11238975
Filing Dt:
09/30/2005
Publication #:
US20070075743
Pub Dt:
04/05/2007
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING CURRENT LEAKAGE REDUCTION SCHEME
32
Patent #:
7369451
Issue Dt:
05/06/2008
Application #:
11261493
Filing Dt:
10/31/2005
Publication #:
US20070097677
Pub Dt:
05/03/2007
Title:
DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS
33
Patent #:
7750695
Issue Dt:
07/06/2010
Application #:
11264283
Filing Dt:
10/31/2005
Publication #:
US20060125535
Pub Dt:
06/15/2006
Title:
PHASE-LOCKED LOOP CIRCUITRY USING CHARGE PUMPS WITH CURRENT MIRROR CIRCUITRY
34
Patent #:
7251148
Issue Dt:
07/31/2007
Application #:
11269659
Filing Dt:
11/09/2005
Publication #:
US20060083041
Pub Dt:
04/20/2006
Title:
MATCHLINE SENSE CIRCUIT AND METHOD
35
Patent #:
7385858
Issue Dt:
06/10/2008
Application #:
11289428
Filing Dt:
11/30/2005
Publication #:
US20070121406
Pub Dt:
05/31/2007
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING LOW POWER CONSUMPTION WITH SELF-REFRESH
36
Patent #:
7277334
Issue Dt:
10/02/2007
Application #:
11295492
Filing Dt:
12/07/2005
Publication #:
US20060083083
Pub Dt:
04/20/2006
Title:
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS
37
Patent #:
7362640
Issue Dt:
04/22/2008
Application #:
11319451
Filing Dt:
12/29/2005
Publication #:
US20070171750
Pub Dt:
07/26/2007
Title:
APPARATUS AND METHOD FOR SELF-REFRESHING DYNAMIC RANDOM ACCESS MEMORY CELLS
38
Patent #:
7761831
Issue Dt:
07/20/2010
Application #:
11322160
Filing Dt:
12/29/2005
Publication #:
US20070157144
Pub Dt:
07/05/2007
Title:
ASIC DESIGN USING CLOCK AND POWER GRID STANDARD CELL
39
Patent #:
7652922
Issue Dt:
01/26/2010
Application #:
11324023
Filing Dt:
12/30/2005
Publication #:
US20070076479
Pub Dt:
04/05/2007
Title:
MULTIPLE INDEPENDENT SERIAL LINK MEMORY
40
Patent #:
7312636
Issue Dt:
12/25/2007
Application #:
11347289
Filing Dt:
02/06/2006
Publication #:
US20070182450
Pub Dt:
08/09/2007
Title:
VOLTAGE LEVEL SHIFTER CIRCUIT
41
Patent #:
7555659
Issue Dt:
06/30/2009
Application #:
11363251
Filing Dt:
02/28/2006
Publication #:
US20070201295
Pub Dt:
08/30/2007
Title:
LOW POWER MEMORY ARCHITECTURE
42
Patent #:
7492656
Issue Dt:
02/17/2009
Application #:
11412783
Filing Dt:
04/28/2006
Publication #:
US20070253268
Pub Dt:
11/01/2007
Title:
DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION
43
Patent #:
7286377
Issue Dt:
10/23/2007
Application #:
11412960
Filing Dt:
04/28/2006
Publication #:
US20070253269
Pub Dt:
11/01/2007
Title:
DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS WITH TEMPERATURE COMPENSATED SELF-REFRESH
44
Patent #:
7478193
Issue Dt:
01/13/2009
Application #:
11419374
Filing Dt:
05/19/2006
Publication #:
US20070008759
Pub Dt:
01/11/2007
Title:
METHOD AND APPARATUS FOR INTERCONNECTING CONTENT ADDRESSABLE MEMORY DEVICES
45
Patent #:
NONE
Issue Dt:
Application #:
11428050
Filing Dt:
06/30/2006
Publication #:
US20080005462
Pub Dt:
01/03/2008
Title:
METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE
46
Patent #:
7742551
Issue Dt:
06/22/2010
Application #:
11495609
Filing Dt:
07/31/2006
Publication #:
US20080025457
Pub Dt:
01/31/2008
Title:
PULSE COUNTER WITH CLOCK EDGE RECOVERY
47
Patent #:
NONE
Issue Dt:
Application #:
11496278
Filing Dt:
07/31/2006
Publication #:
US20070076502
Pub Dt:
04/05/2007
Title:
DAISY CHAIN CASCADING DEVICES WITH INPUT/OUTPUT CONTROL
48
Patent #:
8364861
Issue Dt:
01/29/2013
Application #:
11521734
Filing Dt:
09/15/2006
Publication #:
US20070234071
Pub Dt:
10/04/2007
Title:
ASYNCHRONOUS ID GENERATION
49
Patent #:
8700818
Issue Dt:
04/15/2014
Application #:
11529293
Filing Dt:
09/29/2006
Publication #:
US20080080492
Pub Dt:
04/03/2008
Title:
PACKET BASED ID GENERATION FOR SERIALLY INTERCONNECTED DEVICES
50
Patent #:
7304876
Issue Dt:
12/04/2007
Application #:
11534873
Filing Dt:
09/25/2006
Publication #:
US20070014139
Pub Dt:
01/18/2007
Title:
COMPARE CIRCUIT FOR A CONTENT ADDRESSABLE MEMORY CELL
51
Patent #:
7661010
Issue Dt:
02/09/2010
Application #:
11536709
Filing Dt:
09/29/2006
Publication #:
US20070283182
Pub Dt:
12/06/2007
Title:
APPARATUS AND METHOD FOR INTERFACING TO A MEMORY
52
Patent #:
7391247
Issue Dt:
06/24/2008
Application #:
11550245
Filing Dt:
10/17/2006
Publication #:
US20070063750
Pub Dt:
03/22/2007
Title:
TIMING VERNIER USING A DELAY LOCKED LOOP
53
Patent #:
7511996
Issue Dt:
03/31/2009
Application #:
11565170
Filing Dt:
11/30/2006
Publication #:
US20080130360
Pub Dt:
06/05/2008
Title:
FLASH MEMORY PROGRAM INHIBIT SCHEME
54
Patent #:
7508724
Issue Dt:
03/24/2009
Application #:
11565327
Filing Dt:
11/30/2006
Publication #:
US20080130386
Pub Dt:
06/05/2008
Title:
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
55
Patent #:
7818464
Issue Dt:
10/19/2010
Application #:
11567551
Filing Dt:
12/06/2006
Publication #:
US20080137467
Pub Dt:
06/12/2008
Title:
APPARATUS AND METHOD FOR CAPTURING SERIAL INPUT DATA
56
Patent #:
7515471
Issue Dt:
04/07/2009
Application #:
11583354
Filing Dt:
10/19/2006
Publication #:
US20070153576
Pub Dt:
07/05/2007
Title:
MEMORY WITH OUTPUT CONTROL
57
Patent #:
9240227
Issue Dt:
01/19/2016
Application #:
11594564
Filing Dt:
11/08/2006
Publication #:
US20070109833
Pub Dt:
05/17/2007
Title:
DAISY CHAIN CASCADING DEVICES
58
Patent #:
8069328
Issue Dt:
11/29/2011
Application #:
11606407
Filing Dt:
11/29/2006
Publication #:
US20070233903
Pub Dt:
10/04/2007
Title:
DAISY CHAIN CASCADE CONFIGURATION RECOGNITION TECHNIQUE
59
Patent #:
7915933
Issue Dt:
03/29/2011
Application #:
11606827
Filing Dt:
11/30/2006
Publication #:
US20080130177
Pub Dt:
06/05/2008
Title:
CIRCUIT FOR CLAMPING CURRENT IN A CHARGE PUMP
60
Patent #:
7554855
Issue Dt:
06/30/2009
Application #:
11613325
Filing Dt:
12/20/2006
Publication #:
US20080155185
Pub Dt:
06/26/2008
Title:
HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE MEMORY
61
Patent #:
8984249
Issue Dt:
03/17/2015
Application #:
11613563
Filing Dt:
12/20/2006
Publication #:
US20080155219
Pub Dt:
06/26/2008
Title:
ID GENERATION APPARATUS AND METHOD FOR SERIALLY INTERCONNECTED DEVICES
62
Patent #:
8271758
Issue Dt:
09/18/2012
Application #:
11622828
Filing Dt:
01/12/2007
Publication #:
US20110087823
Pub Dt:
04/14/2011
Title:
APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE
63
Patent #:
8010709
Issue Dt:
08/30/2011
Application #:
11624929
Filing Dt:
01/19/2007
Publication #:
US20080140948
Pub Dt:
06/12/2008
Title:
APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE
64
Patent #:
7529149
Issue Dt:
05/05/2009
Application #:
11637175
Filing Dt:
12/12/2006
Publication #:
US20080137461
Pub Dt:
06/12/2008
Title:
MEMORY SYSTEM AND METHOD WITH SERIAL AND PARALLEL MODES
65
Patent #:
NONE
Issue Dt:
Application #:
11639375
Filing Dt:
12/14/2006
Publication #:
US20070165457
Pub Dt:
07/19/2007
Title:
Nonvolatile memory system
66
Patent #:
7747833
Issue Dt:
06/29/2010
Application #:
11643850
Filing Dt:
12/22/2006
Publication #:
US20070143677
Pub Dt:
06/21/2007
Title:
INDEPENDENT LINK AND BANK SELECTION
67
Patent #:
7459949
Issue Dt:
12/02/2008
Application #:
11668862
Filing Dt:
01/30/2007
Publication #:
US20080180144
Pub Dt:
07/31/2008
Title:
PHASE DETECTOR CIRCUIT AND METHOD THEREFOR
68
Patent #:
7334093
Issue Dt:
02/19/2008
Application #:
11673703
Filing Dt:
02/12/2007
Publication #:
US20070136514
Pub Dt:
06/14/2007
Title:
BLOCK PROGRAMMABLE PRIORITY ENCODER IN A CAM
69
Patent #:
7509469
Issue Dt:
03/24/2009
Application #:
11673834
Filing Dt:
02/12/2007
Publication #:
US20070186034
Pub Dt:
08/09/2007
Title:
SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
70
Patent #:
7551012
Issue Dt:
06/23/2009
Application #:
11691849
Filing Dt:
03/27/2007
Publication #:
US20080238534
Pub Dt:
10/02/2008
Title:
PHASE SHIFTING IN DLL/PLL
71
Patent #:
7853727
Issue Dt:
12/14/2010
Application #:
11692446
Filing Dt:
03/28/2007
Publication #:
US20080192649
Pub Dt:
08/14/2008
Title:
APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION
72
Patent #:
8331361
Issue Dt:
12/11/2012
Application #:
11692452
Filing Dt:
03/28/2007
Publication #:
US20110032932
Pub Dt:
02/10/2011
Title:
APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE
73
Patent #:
7802064
Issue Dt:
09/21/2010
Application #:
11693027
Filing Dt:
03/29/2007
Publication #:
US20070233939
Pub Dt:
10/04/2007
Title:
FLASH MEMORY SYSTEM CONTROL SCHEME
74
Patent #:
7705642
Issue Dt:
04/27/2010
Application #:
11703634
Filing Dt:
02/08/2007
Publication #:
US20080191782
Pub Dt:
08/14/2008
Title:
SIMPLIFIED BIAS CIRCUITRY FOR DIFFERENTIAL BUFFER STAGE WITH SYMMETRIC LOADS
75
Patent #:
7577059
Issue Dt:
08/18/2009
Application #:
11711043
Filing Dt:
02/27/2007
Publication #:
US20080205164
Pub Dt:
08/28/2008
Title:
DECODING CONTROL WITH ADDRESS TRANSITION DETECTION IN PAGE ERASE FUNCTION
76
Patent #:
7551492
Issue Dt:
06/23/2009
Application #:
11715838
Filing Dt:
03/08/2007
Publication #:
US20070230253
Pub Dt:
10/04/2007
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY WITH PAGE ERASE
77
Patent #:
7348804
Issue Dt:
03/25/2008
Application #:
11732181
Filing Dt:
04/02/2007
Publication #:
US20070176639
Pub Dt:
08/02/2007
Title:
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
78
Patent #:
7679418
Issue Dt:
03/16/2010
Application #:
11741383
Filing Dt:
04/27/2007
Publication #:
US20080265970
Pub Dt:
10/30/2008
Title:
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Title:
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Title:
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Title:
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Assignor
1
MOSAID TECHNOLOGIES INCORPORATED
Exec Dt:
02/09/2009
Assignee
1
MOSAID TECHNOLOGIES INCORPORATED
11 HINES ROAD
SUITE 203
OTTAWA, CANADA K2K 2X1
Correspondence name and address
MOSAID TECHNOLOGIES INCORPORATED
11 HINES ROAD
SUITE 203
OTTAWA, K2K 2X1 CANADA

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