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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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09930598
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Filing Dt:
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08/15/2001
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Publication #:
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Pub Dt:
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02/28/2002
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Title:
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METHOD, SYSTEM AND COMPUTER PROGRAM FOR SYNTAX VALIDATION
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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10068789
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Filing Dt:
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02/05/2002
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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DYNAMIC MEMORY REFRESH CIRCUITRY
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10094793
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Filing Dt:
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03/11/2002
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Publication #:
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Pub Dt:
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09/11/2003
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Title:
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DYNAMIC DELAY LINE CONTROL
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10095318
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Filing Dt:
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03/11/2002
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Publication #:
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Pub Dt:
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09/11/2003
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Title:
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METHOD AND APPARATUS FOR A DELAY LOCK LOOP
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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10095730
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Filing Dt:
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03/12/2002
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Publication #:
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Pub Dt:
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02/13/2003
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Title:
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METHOD OF RECOVERING A FLIGHT CRITICAL COMPUTER AFTER A RADIATION EVENT
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10100639
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Filing Dt:
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03/19/2002
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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DELAY LOCK LOOP HAVING AN EDGE DETECTOR AND FIXED DELAY
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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10100713
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Filing Dt:
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03/19/2002
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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DELAY LOCK LOOP HAVING A VARIABLE VOLTAGE REGULATOR
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10102546
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Filing Dt:
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03/20/2002
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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SYSTEM AND METHOD FOR ENHANCED MONITORING OF AN ETCH PROCESS
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10113386
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Filing Dt:
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03/29/2002
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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METHOD AND APPARATUS FOR PROVIDING ADJUSTABLE LATENCY FOR TEST MODE COMPRESSION
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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10125118
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Filing Dt:
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04/18/2002
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Title:
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SPACER ASSISTED TRENCH TOP ISOLATION FOR VERTICAL DRAM'S
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10133764
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Filing Dt:
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04/26/2002
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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REDUNDANCY IN CHAINED MEMORY ARCHITECTURES
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10135144
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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03/04/2004
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Title:
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INTERNAL GENERATION OF REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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10138396
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Filing Dt:
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05/03/2002
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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LAYOUT FOR THERMALLY SELECTED CROSS-POINT MRAM CELL
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Patent #:
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Issue Dt:
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01/25/2005
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Application #:
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10143673
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Filing Dt:
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05/10/2002
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Publication #:
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Pub Dt:
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11/13/2003
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Title:
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METHOD OF FORMING SURFACE-SMOOTHING LAYER FOR SEMICONDUCTOR DEVICES WITH MAGNETIC MATERIAL LAYERS
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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10146976
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Filing Dt:
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05/16/2002
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Title:
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METHOD OF MANUFACTURING MRAM OFFSET CELLS IN A DAMASCENE STRUCTURE
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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10153042
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Filing Dt:
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05/22/2002
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Publication #:
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Pub Dt:
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11/27/2003
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Title:
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PARTIAL REFRESH FOR SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) CIRCUITS
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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10159169
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Filing Dt:
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05/31/2002
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Title:
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SUPPORT LINER FOR ISOLATION TRENCH HEIGHT CONTROL IN VERTICAL DRAM PROCESSING
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10161867
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Filing Dt:
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06/03/2002
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Publication #:
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Pub Dt:
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12/04/2003
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Title:
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LITHOGRAPHY ALIGNMENT AND OVERLAY MEASUREMENT MARKS FORMED BY RESIST MASK BLOCKING FOR MRAMS
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10161908
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Filing Dt:
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06/04/2002
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Publication #:
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Pub Dt:
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12/04/2003
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Title:
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FERROELECTRIC MEMORY INTEGRATED CIRCUIT WITH IMPROVED RELIABILITY
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10171255
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Filing Dt:
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06/12/2002
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Publication #:
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Pub Dt:
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12/18/2003
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Title:
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VERTICAL ACCESS TRANSISTOR WITH CURVED CHANNEL
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10174727
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Filing Dt:
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06/19/2002
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Publication #:
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Pub Dt:
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12/25/2003
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Title:
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FUSE CONFIGURATION WITH MODIFIED CAPACITOR BORDER LAYOUT FOR A SEMICONDUCTOR STORAGE DEVICE
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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10180254
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Filing Dt:
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06/26/2002
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Publication #:
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Pub Dt:
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01/01/2004
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Title:
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CURRENT MEASUREMENT CIRCUIT AND METHOD FOR VOLTAGE REGULATED SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10223511
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Filing Dt:
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08/19/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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DRAM HAVING IMPROVED LEAKAGE PERFORMANCE AND METHOD FOR MAKING SAME
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10232786
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
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Title:
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METHOD OF FORMING A GATE CONTACT IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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10241032
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Filing Dt:
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09/11/2002
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Publication #:
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Pub Dt:
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03/11/2004
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Title:
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CIRCUIT AND METHOD FOR TESTING EMBEDDED DRAM CIRCUITS THROUGH DIRECT ACCESS MODE
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10248949
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Filing Dt:
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03/05/2003
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Publication #:
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Pub Dt:
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09/23/2004
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Title:
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METHOD OF PLANARIZING SUBSTRATES
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10248950
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Filing Dt:
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03/05/2003
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Publication #:
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Pub Dt:
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09/09/2004
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Title:
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METHOD OF DETERMINING THE ENDPOINT OF A PLANARIZATION PROCESS
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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10253148
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Filing Dt:
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09/24/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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TOPOGRAPHY CORRECTION FOR TESTING OF REDUNDANT ARRAY ELEMENTS
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10254305
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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DQS POSTAMBLE NOISE SUPPRESSION BY FORCING A MINIMUM PULSE LENGTH
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10255015
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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RAPID DEPOSITION OF BOROSILICATE GLASS FILMS
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10256181
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Filing Dt:
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09/26/2002
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Title:
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SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF USING ROW COMPRESSION TEST MODE
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10265964
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Filing Dt:
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10/07/2002
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Publication #:
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Pub Dt:
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04/08/2004
| | | | |
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Title:
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BANK ADDRESS MAPPING ACCORDING TO BANK RETENTION TIME IN DYNAMIC RANDOM ACCESS MEMORIES
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10267262
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Filing Dt:
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10/09/2002
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Publication #:
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Pub Dt:
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04/22/2004
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Title:
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VOLTAGE REGULATOR WITH DISTRIBUTED OUTPUT TRANSISTOR
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10285027
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Filing Dt:
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10/31/2002
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Publication #:
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Pub Dt:
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05/06/2004
| | | | |
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Title:
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MEMORY DEVICE WITH COLUMN SELECT BEING VARIABLY DELAYED
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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10289075
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Filing Dt:
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11/06/2002
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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USING ISOLATED P-WELL TRANSISTOR ARRANGEMENTS TO AVOID LEAKAGE CAUSED BY WORD LINE/BIT LINE SHORTS
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Patent #:
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Issue Dt:
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04/08/2008
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Application #:
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10304506
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Filing Dt:
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11/26/2002
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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MODULAR TEST CONTROLLER WITH BISTCIRCUIT FOR TESTING EMBEDDED DRAM CIRCUITS
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10320867
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Filing Dt:
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12/17/2002
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Title:
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SELF-ALIGNED CONTACT FORMATION USING DOUBLE SIN SPACERS
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10387993
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Filing Dt:
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03/13/2003
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Publication #:
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Pub Dt:
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09/16/2004
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Title:
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CIRCUIT TECHNIQUE FOR COLUMN REDUNDANCY FUSE LATCHES
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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10396966
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Filing Dt:
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03/25/2003
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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REGISTER FOR THE PARALLEL-SERIAL CONVERSION OF DATA
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10401185
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Filing Dt:
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03/27/2003
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Publication #:
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Pub Dt:
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10/02/2003
| | | | |
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Title:
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INSTALLATION FOR PROCESSING A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING THE INSTALLATION
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10413812
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Filing Dt:
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04/15/2003
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
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Title:
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METHOD AND CONFIGURATION FOR REINFORCEMENT OF A DIELECTRIC LAYER AT DEFECTS BY SELF-ALIGNING AND SELF-LIMITING ELECTROCHEMICAL CONVERSION OF A SUBSTRATE MATERIAL
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10413814
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Filing Dt:
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04/15/2003
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Publication #:
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Pub Dt:
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10/16/2003
| | | | |
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Title:
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METHOD AND DEVICE FOR GENERATING A REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10414837
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Filing Dt:
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04/16/2003
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Publication #:
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Pub Dt:
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10/16/2003
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Title:
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SEMICONDUCTOR ASSEMBLY WITH A SEMICONDUCTOR MODULE
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Patent #:
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Issue Dt:
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06/19/2007
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Application #:
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10423812
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Filing Dt:
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04/25/2003
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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CIRCUIT CONFIGURATION AND METHOD FOR TRANSMITTING DIGITAL SIGNALS
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Patent #:
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Issue Dt:
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07/05/2005
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Application #:
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10424347
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Filing Dt:
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04/28/2003
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Publication #:
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Pub Dt:
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01/22/2004
| | | | |
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Title:
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SYSTEM AND METHOD FOR THE FUNCTIONAL TESTING OF SEMICONDUCTOR MEMORY CHIPS
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10424376
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Filing Dt:
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04/28/2003
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Publication #:
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Pub Dt:
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02/12/2004
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Title:
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METHODS FOR PRODUCING A DIELECTRIC, DIELECTRIC HAVING SELF-GENERATING PORES, MONOMER FOR POROUS DIELECTRICS, PROCESS FOR PREPARING POLY-O-HYDROXYAMIDES, PROCESS FOR PREPARING POLYBENZOXAZOLES, AND PROCESSES FOR PRODUCING AN ELECTRONIC COMPONENT
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10425002
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Filing Dt:
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04/28/2003
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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READING EXTENDED DATA BURST FROM MEMORY
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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10425461
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Filing Dt:
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04/29/2003
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Publication #:
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Pub Dt:
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02/12/2004
| | | | |
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Title:
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METHOD FOR PATTERNING CERAMIC LAYERS
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10429158
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Filing Dt:
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05/02/2003
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Publication #:
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Pub Dt:
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01/08/2004
| | | | |
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Title:
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STORAGE CIRCUIT
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Patent #:
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Issue Dt:
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04/05/2005
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Application #:
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10429578
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Filing Dt:
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05/05/2003
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Publication #:
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Pub Dt:
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11/27/2003
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Title:
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TEST CONFIGURATION WITH AUTOMATIC TEST MACHINE AND INTEGRATED CIRCUIT AND METHOD FOR DETERMINING THE TIME BEHAVIOR OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10431425
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Filing Dt:
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05/06/2003
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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METHOD FOR FABRICATING A TRANSISTOR WITH A GATE STRUCTURE
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10439085
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Filing Dt:
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05/15/2003
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Publication #:
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Pub Dt:
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01/15/2004
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Title:
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MEMORY SYSTEM
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10440480
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Filing Dt:
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05/15/2003
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Publication #:
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Pub Dt:
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01/15/2004
| | | | |
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Title:
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METHOD FOR CONNECTING CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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10441609
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Filing Dt:
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05/20/2003
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Publication #:
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Pub Dt:
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03/31/2005
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Title:
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TESTING MEMORY UNITS IN A DIGITAL CIRCUIT
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10442739
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
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12/18/2003
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Title:
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PHOTOLITHOGRAPHIC MASK HAVING A STRUCTURE REGION COVERED BY A THIN PROTECTIVE COATING OF ONLY A FEW ATOMIC LAYERS AND METHODS FOR THE FABRICATION OF THE MASK INCLUDING ALCVD TO FORM THE THIN PROTECTIVE COATING
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11/02/2004
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10444542
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05/23/2003
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11/27/2003
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Title:
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INTEGRATED MEMORY HAVING AN ACCELERATED WRITE CYCLE
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12/27/2005
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10446396
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05/28/2003
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01/22/2004
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CONNECTION OF INTEGRATED CIRCUITS
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05/11/2004
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10446601
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05/28/2003
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12/04/2003
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INTEGRATED MEMORY USING PREFETCH ARCHITECTURE AND METHOD FOR OPERATING AN INTEGRATED MEMORY
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02/17/2004
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10446995
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05/27/2003
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Pub Dt:
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11/27/2003
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Title:
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CIRCUIT CONFIGURATION HAVING A FLOW CONTROLLER, INTEGRATED MEMORY DEVICE, AND TEST CONFIGURATION HAVING SUCH A CIRCUIT CONFIGURATION
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04/17/2007
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10447386
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05/29/2003
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02/05/2004
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Title:
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METHOD FOR CLASSIFYING ERRORS IN THE LAYOUT OF A SEMICONDUCTOR CIRCUIT
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06/07/2005
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10452477
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06/02/2003
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02/19/2004
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Title:
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CIRCUIT CONFIGURATION FOR SETTING THE INPUT RESISTANCE AND THE INPUT CAPACITANCE OF AN INTEGRATED SEMICONDUCTOR CIRCUIT CHIP
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09/12/2006
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10452485
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06/02/2003
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12/04/2003
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Title:
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TEST DEVICE, TEST SYSTEM AND METHOD FOR TESTING A MEMORY CIRCUIT
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10/19/2004
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10460715
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06/12/2003
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01/29/2004
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Title:
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ZIPPER CONNECTOR
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08/30/2005
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10462419
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06/16/2003
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12/18/2003
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Title:
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SEMICONDUCTOR MEMORY WITH ADDRESS DECODING UNIT, AND ADDRESS LOADING METHOD
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08/23/2005
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10462512
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06/16/2003
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12/18/2003
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Title:
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METHOD FOR PATTERNING A LAYER OF SILICON, AND METHOD FOR FABRICATING AN INTEGRATED SEMICONDUCTOR CIRCUIT
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07/12/2005
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10464429
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06/18/2003
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02/26/2004
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Title:
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CONNECTION OF INTEGRATED CIRCUIT TO A SUBSTRATE
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07/19/2005
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10464611
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06/18/2003
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04/22/2004
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VOLTAGE REGULATOR
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01/11/2005
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10465488
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06/19/2003
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02/05/2004
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Title:
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METHOD FOR FABRICATING A DEEP TRENCH CAPACITOR FOR DYNAMIC MEMORY CELLS
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12/18/2007
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10509553
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05/17/2005
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09/22/2005
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MRAM MEMORY CELL WITH A REFERENCE LAYER AND METHOD FOR FABRICATING
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06/10/2008
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10518141
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10/07/2005
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06/29/2006
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Title:
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PACKAGE FOR SEMICONDUCTOR COMPONENTS AND METHOD FOR PRODUCING THE SAME
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11/13/2007
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10519444
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08/26/2005
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03/02/2006
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ELECTRONIC COMPONENT WITH MULTILAYERED REWIRING PLATE AND METHOD FOR PRODUCING THE SAME
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07/08/2008
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10519741
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11/04/2005
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05/04/2006
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Title:
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METHOD FOR CONTACTING PARTS OF A COMPONENT INTEGRATED INTO A SEMICONDUCTOR SUBSTRATE
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05/20/2008
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10520534
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01/06/2005
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03/23/2006
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POLYMERIZABLE COMPOSITIONS; POLYMER, RESIST, AND LITHOGRAPHY METHOD
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10/14/2008
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10607518
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06/26/2003
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01/15/2004
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METHOD FOR CHECKING THE REFRESH FUNCTION OF AN INFORMATION MEMORY
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07/17/2007
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10609453
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06/27/2003
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04/29/2004
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Title:
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POLY-O-HYDROXYAMIDE, POLYBENZOXAZOLE FROM THE POLY-O-HYDROXYAMIDE, ELECTRONIC COMPONENT INCLUDING A POLYBENZOXAZOLE, AND PROCESSES FOR PRODUCING THE SAME
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12/28/2004
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10609455
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06/27/2003
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02/12/2004
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CONFIGURATION FOR TESTING SEMICONDUCTOR DEVICES
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03/01/2005
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10609456
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06/27/2003
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03/11/2004
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BIS-O-AMINOPHENOLS AND PROCESSES FOR PRODUCING BIS-O-AMINOPHENOLS
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10/19/2004
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10609460
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06/27/2003
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04/01/2004
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Title:
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POLY-O-HYDROXYAMIDE, POLYBENZOXAZOLE, AND ELECTRONIC COMPONENT INCLUDING A DIELECTRIC HAVING A BARRIER EFFECT AGAINST COPPER DIFFUSION, AND PROCESSES FOR PREPARING POLY-O-HYDROXYAMIDES, POLYBENZOXAZOLES, AND ELECTRONIC COMPONENTS
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07/19/2005
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10609871
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06/30/2003
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04/08/2004
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CONFIGURATION, PLUG-IN MOUNT AND CONTACT ELEMENT FOR FIXING AND CONTACTING SWITCHING ASSEMBLIES ON A SUBSTRATE
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03/07/2006
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10609873
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06/30/2003
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01/08/2004
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METHOD, ADAPTER CARD AND CONFIGURATION FOR AN INSTALLATION OF MEMORY MODULES
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01/11/2005
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10610241
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06/30/2003
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03/11/2004
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CONNECTOR FOR A PLURALITY OF SWITCHING ASSEMBLIES WITH COMPATIBLE INTERFACES
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03/27/2007
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10613367
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07/03/2003
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01/22/2004
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TEST CIRCUIT AND METHOD FOR TESTING AN INTEGRATED MEMORY CIRCUIT
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10/11/2005
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10613381
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07/03/2003
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04/22/2004
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02/08/2005
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10619014
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07/11/2003
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01/22/2004
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CIRCUIT CONFIGURATION FOR CONTROLLING LOAD-DEPENDENT DRIVER STRENGTHS
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12/11/2007
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10619157
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07/14/2003
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08/05/2004
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INTEGRATED MEMORY AND METHOD FOR TESTING THE MEMORY
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11/09/2004
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10619290
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07/15/2003
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02/19/2004
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CIRCUIT CONFIGURATION FOR THE BIT-PARALLEL OUTPUTTING OF A DATA WORD
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06/15/2004
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10619970
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07/15/2003
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01/22/2004
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INTEGRATED SEMICONDUCTOR MEMORY AND FABRICATION METHOD
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07/05/2005
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10620092
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07/15/2003
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CIRCUIT ELEMENT WITH TIMING CONTROL
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04/04/2006
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10620570
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07/16/2003
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01/22/2004
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PVD METHOD AND PVD APPARATUS
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03/22/2005
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10620587
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07/16/2003
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04/29/2004
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CONFIGURATION AND METHOD FOR CHECKING AN ADDRESS GENERATOR
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08/29/2006
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10621535
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07/17/2003
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04/14/2005
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METHOD FOR CORRECTING LOCAL LOADING EFFECTS IN THE ETCHING OF PHOTOMASKS
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02/20/2007
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10622050
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07/17/2003
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03/18/2004
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WAFER LIFTING DEVICE
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01/31/2006
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10623067
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07/18/2003
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02/19/2004
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METHOD OF GENERATING A TEST PATTERN FOR SIMULATING AND/OR TESTING THE LAYOUT OF AN INTEGRATED CIRCUIT
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02/22/2005
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10623831
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07/21/2003
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02/12/2004
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CIRCUIT AND METHOD FOR WRITING AND READING DATA FROM A DYNAMIC MEMORY CIRCUIT
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05/03/2005
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10625495
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07/23/2003
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07/08/2004
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METHOD FOR CONNECTING AN INTEGRATED CIRCUIT TO A SUBSTRATE AND CORRESPONDING CIRCUIT ARRANGEMENT
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11/22/2005
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10626955
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07/25/2003
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02/05/2004
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Title:
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INTEGRATED SYNCHRONOUS MEMORY AND MEMORY CONFIGURATION HAVING A MEMORY MODULE WITH AT LEAST ONE SYNCHRONOUS MEMORY
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02/01/2005
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10626957
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07/25/2003
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01/29/2004
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SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD FOR FABRICATING THE SEMICONDUCTOR CIRCUIT STRUCTURE
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11/02/2004
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10627841
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07/25/2003
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08/12/2004
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CIRCUIT CONFIGURATION FOR READING OUT A PROGRAMMABLE LINK
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11/23/2004
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10627906
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07/25/2003
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04/29/2004
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POLYMERIZABLE COMPOSITION, POLYMER, RESIST, AND PROCESS FOR ELECTRON BEAM LITHOGRAPHY
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07/19/2005
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10630373
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07/30/2003
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Pub Dt:
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07/01/2004
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Title:
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SEMICONDUCTOR TRENCH STRUCTURE
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