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Reel/Frame:027233/0886   Pages: 19
Recorded: 11/16/2011
Attorney Dkt #:HYNIX
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 15
1
Patent #:
Issue Dt:
08/22/2000
Application #:
08744805
Filing Dt:
11/06/1996
Title:
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A TAPERED CONTACT HOLE
2
Patent #:
Issue Dt:
07/11/2000
Application #:
08943184
Filing Dt:
10/03/1997
Title:
CLOCK SIGNAL PHASE COMPARATOR
3
Patent #:
Issue Dt:
01/25/2000
Application #:
09006479
Filing Dt:
01/13/1998
Title:
METHOD FOR FABRICATING FIELD EFFECT TRANSISTOR
4
Patent #:
Issue Dt:
09/12/2000
Application #:
09013095
Filing Dt:
01/26/1998
Title:
PLANARIZATION METHOD FOR A SEMICONDUCTOR DEVICE
5
Patent #:
Issue Dt:
11/07/2000
Application #:
09317113
Filing Dt:
05/24/1999
Title:
SENSE AMPLIFIER DRIVING DEVICE
6
Patent #:
Issue Dt:
05/21/2002
Application #:
09427272
Filing Dt:
10/26/1999
Title:
ANALOG MIXED DIGITAL DLL
7
Patent #:
Issue Dt:
03/18/2003
Application #:
09749621
Filing Dt:
12/28/2000
Publication #:
Pub Dt:
09/06/2001
Title:
SEMICONDUCTOR MEMORY DEVICE HAVING CAPACITOR STRUCTURE FORMED IN PROXIMITY TO CORRESPONDING TRANSISTOR
8
Patent #:
Issue Dt:
02/18/2003
Application #:
09750017
Filing Dt:
12/29/2000
Publication #:
Pub Dt:
09/20/2001
Title:
COLUMN TRANSISTOR FOR SEMICONDUCTOR DEVICES
9
Patent #:
Issue Dt:
10/29/2002
Application #:
10034242
Filing Dt:
12/28/2001
Title:
METHOD OF FORMING A CONTACT PLUG FOR A SEMICONDUCTOR DEVICE
10
Patent #:
Issue Dt:
05/20/2003
Application #:
10177950
Filing Dt:
06/21/2002
Publication #:
Pub Dt:
12/26/2002
Title:
METHOD OF FORMING CONTACT HOLES IN SEMICONDUCTOR DEVICES AND METHOD OF FORMING CAPACITORS USING THE SAME
11
Patent #:
Issue Dt:
02/22/2005
Application #:
10883099
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
02/24/2005
Title:
APPARATUS AND METHOD OF COMPENSATING FOR PHASE DELAY IN SEMICONDUCTOR DEVICE
12
Patent #:
Issue Dt:
08/29/2006
Application #:
11004806
Filing Dt:
12/07/2004
Publication #:
Pub Dt:
03/09/2006
Title:
SEMICONDUCTOR MEMORY DEVICE
13
Patent #:
Issue Dt:
09/13/2005
Application #:
11026970
Filing Dt:
12/30/2004
Title:
DELAY LOCKED LOOP AND LOCKING METHOD THEREOF
14
Patent #:
Issue Dt:
05/01/2007
Application #:
11077612
Filing Dt:
03/11/2005
Publication #:
Pub Dt:
06/29/2006
Title:
CLOCK SIGNAL GENERATION APPARATUS FOR USE IN SEMICONDUCTOR MEMORY DEVICE AND ITS METHOD
15
Patent #:
Issue Dt:
11/21/2006
Application #:
11293124
Filing Dt:
12/05/2005
Publication #:
Pub Dt:
04/20/2006
Title:
METHOD OF INHIBITING DEGRADATION OF GATE OXIDE FILM
Assignor
1
Exec Dt:
08/22/2011
Assignee
1
44 CHIPMAN HILL
SUITE 1000
SAINT JOHN, NB, CANADA E2L 2A9
Correspondence name and address
MOSAID CORPORATION LTD.
5700 GRANITE PARKWAY
SUITE 960
PLANO, TX 75024

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