Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 005253/0892 | |
| Pages: | 1 |
| | Recorded: | 02/28/1990 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST. |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
07/17/1990
|
Application #:
|
07119919
|
Filing Dt:
|
11/13/1987
|
Title:
|
MICROPROCESSOR WITH A CACHE MEMORY IN WHICH VALIDITY FLAGS FOR FIRST AND SECOND DATA AREAS ARE SIMULTANEOUSLY READABLE
|
|
Assignees
|
|
|
6 KANDA SURUGADAI 4-CHOME, CHIYODA-KU |
TOKYO, JAPAN |
|
|
|
1479, JOUSUIHONCHO, KODAIRA-SHI |
TOKYO, JAPAN |
|
Correspondence name and address
|
|
ANTONELLI, TERRY & WANDS
|
|
SUITE 600
|
|
1919 PENNSYLVANIA AVENUE, N.W.
|
|
WASHINGTON, DC 20006
|
Search Results as of:
09/26/2024 09:40 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|