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Total properties:
42
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Patent #:
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Issue Dt:
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10/19/1993
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Application #:
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07679370
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Filing Dt:
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04/02/1991
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Title:
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FULLY CONFIGURABLE VERSATILE FIELD PROGRAMMABLE FUNCTION ELEMENT
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Patent #:
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Issue Dt:
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08/24/1993
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Application #:
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07797648
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Filing Dt:
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11/25/1991
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Title:
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MULTIPLE VOLTAGE SUPPLIES FOR FIELD PROGRAMMABLE GATE ARRAYS AND THE LIKE
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Patent #:
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Issue Dt:
|
01/24/1995
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Application #:
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07971501
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Filing Dt:
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11/04/1992
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Title:
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LOW-SKEW SIGNAL ROUTING IN A PROGRAMMABLE ARRAY
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Patent #:
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Issue Dt:
|
03/07/1995
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Application #:
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08019963
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Filing Dt:
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02/19/1993
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Title:
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FPGA WITH DISTRIBUTED SWITCH MATRIX
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Patent #:
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Issue Dt:
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05/10/1994
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Application #:
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08037766
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Filing Dt:
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03/26/1993
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Title:
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FIELD PROGRAMMABLE GATE ARRAY WITH DIRECT INPUT/OUTPUT CONNECTION
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Patent #:
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Issue Dt:
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01/10/1995
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Application #:
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08065823
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Filing Dt:
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05/21/1993
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Title:
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FPGA HAVING PFU WITH PROGRAMMABLE OUTPUT DRIVER INPUTS
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Patent #:
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Issue Dt:
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01/31/1995
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Application #:
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08113154
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Filing Dt:
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08/27/1993
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Title:
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PROGRAMMABLE FUNCTION UNIT WITH PROGRAMMABLE FAST RIPPLE LOGIC
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Patent #:
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Issue Dt:
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02/28/1995
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Application #:
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08163952
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Filing Dt:
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12/08/1993
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Title:
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APPARATUS AND METHOD TO IMPROVE PROGRAMMING SPEED OF FIELD PROGRAMMABLE GATE ARRAYS
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Patent #:
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Issue Dt:
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08/15/1995
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Application #:
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08304013
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Filing Dt:
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09/09/1994
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Title:
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FIELD PROGRAMMABLE GATE ARRAY USING LOOK-UPTABLES, MULTIPLEXERS AND DECODERS
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Patent #:
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Issue Dt:
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01/14/1997
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Application #:
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08473620
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Filing Dt:
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06/07/1995
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Title:
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SYSTEM FOR SYNTHESIZING FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS FROM HIGH LEVEL CIRCUIT DESCRIPTIONS
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Patent #:
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Issue Dt:
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06/11/1996
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Application #:
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08492604
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Filing Dt:
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06/20/1995
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Title:
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METHOD AND APPARATUS FOR CONVERTING FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS INTO MAS-PROGRAMMABLE LOGIC CELL IMPLEMENTATIONS
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Patent #:
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Issue Dt:
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10/29/1996
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Application #:
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08507893
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Filing Dt:
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07/27/1995
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Title:
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PROGRAMMABLE FUNCTION UNIT AS PARALLEL MULTIPLIER CELL
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Patent #:
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Issue Dt:
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09/24/1996
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Application #:
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08507957
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Filing Dt:
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07/27/1995
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Title:
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FIELD PROGRAMMABLE GATE ARRAY WITH MULTI-PORT RAM
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Patent #:
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Issue Dt:
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06/18/1996
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Application #:
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08535362
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Filing Dt:
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09/28/1995
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Title:
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LOW-SKEW SIGNAL ROUTING IN A PROGRAMMABLE ARRAY
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|
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Patent #:
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Issue Dt:
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04/22/1997
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Application #:
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08606702
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Filing Dt:
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02/26/1996
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Title:
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FIELD PROGRAMMABLE GATE ARRAY WITH WRITE-PORT ENABLED MEMORY
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Patent #:
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Issue Dt:
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01/19/1999
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Application #:
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08710445
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Filing Dt:
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09/17/1996
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Title:
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CONFIGURATION PIN EMULATION CIRCUIT FOR A FIELD PROGRAMMABLE GATE ARRAY
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Patent #:
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|
Issue Dt:
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11/23/1999
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Application #:
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08729117
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Filing Dt:
|
10/11/1996
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Title:
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METHOD FOR TESTING FIELD PROGRAMMABLE GATE ARRAYS
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|
|
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08748041
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Filing Dt:
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11/12/1996
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Title:
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FPGA-BASED PROCESSOR
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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08781882
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Filing Dt:
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01/10/1997
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|
Title:
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TIMED CIRCUIT SIMULATION IN HARDWARE USING FPGA'S
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|
|
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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08899428
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Filing Dt:
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07/24/1997
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Title:
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FPGA HAVING PREDICTABLE OPEN-DRAIN DRIVE MODE
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|
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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08938550
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Filing Dt:
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09/26/1997
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|
Title:
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HYBRID PROGRAMMABLE GATE ARRAYS
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|
|
|
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Patent #:
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|
Issue Dt:
|
02/22/2000
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Application #:
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08949992
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Filing Dt:
|
10/15/1997
|
|
Title:
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PROGRAMMABLE CLOCK MANAGER FOR A PROGRAMMABLE LOGIC DEVICE THAT CAN GENERATE AT LEAST TWO DIFFERENT OUTPUT CLOCKS
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|
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Patent #:
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|
Issue Dt:
|
04/10/2001
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Application #:
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08950444
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Filing Dt:
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10/15/1997
|
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Title:
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FIELD PROGRAMMABLE GATE ARRAY HAVING A DEDICATED PROCESSOR INTERFACE
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|
|
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Patent #:
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|
Issue Dt:
|
11/16/1999
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Application #:
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08950446
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Filing Dt:
|
10/15/1997
|
|
Title:
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BI-DIRECTIONAL BUFFERS AND SUPPLEMENTAL LOGIC AND INTERCONNECT CELLS FOR PROGRAMMABLE LOGIC DEVICES
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|
|
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Patent #:
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|
Issue Dt:
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05/09/2000
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Application #:
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08950448
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Filing Dt:
|
10/15/1997
|
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Title:
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PROGRAMMABLE CLOCK MANAGER FOR A PROGRAMMABLE LOGIC DEVICE THAT CAN BE PROGRAMMED WITHOUT RECONFIGURING THE DEVICE
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|
|
|
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Patent #:
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|
Issue Dt:
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04/11/2000
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Application #:
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08950624
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Filing Dt:
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10/15/1997
|
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH LOGIC CELLS HAVING A FLEXIBLE INPUT STRUCTURE
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|
|
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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08951128
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Filing Dt:
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10/15/1997
|
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Title:
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PROGRAMMABLE CLOCK MANAGER FOR A PROGRAMMABLE LOGIC DEVICE THAT CAN IMPLEMENT DELAY-LOCKED LOOP FUNCTIONS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
12/14/1999
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Application #:
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08974799
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Filing Dt:
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11/20/1997
|
|
Title:
|
METHOD FOR TESTING FIELD PROGRAMMABLE GATE ARRAYS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/07/2000
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Application #:
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09010000
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Filing Dt:
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01/21/1998
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|
Title:
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VIRTUAL LOGIC SYSTEM FOR RECONFIGURABLE HARDWARE
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/16/2000
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Application #:
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09045128
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Filing Dt:
|
03/20/1998
|
|
Title:
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GLOBAL SIGNAL DISTRIBUTION WITH REDUCED ROUTING TRACKS IN AN FPGA
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/22/2000
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Application #:
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09059552
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Filing Dt:
|
04/13/1998
|
|
Title:
|
METHOD OF TESTING AND DIAGNOSING FIELD PROGRAMMABLE GATE ARRAYS
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|
|
|
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Patent #:
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|
Issue Dt:
|
12/14/1999
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Application #:
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09069768
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Filing Dt:
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04/30/1998
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Title:
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NON-VOLATILE MEMORY ELEMENT FOR PROGRAMMABLE LOGIC APPLICATIONS AND OPERATIONAL METHODS THEREFOR
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|
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09109123
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Filing Dt:
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06/30/1998
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|
Title:
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METHOD AND APPARATUS FOR TESTING FIELD PROGRAMMABLE GATE ARRAYS
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|
|
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Patent #:
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Issue Dt:
|
09/26/2000
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Application #:
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09115683
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Filing Dt:
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07/15/1998
|
|
Title:
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SIGNALING VOLTAGE RANGE DISCRIMINATOR
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|
|
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Patent #:
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|
Issue Dt:
|
02/12/2002
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Application #:
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09169848
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Filing Dt:
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10/09/1998
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Title:
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TEST CIRCUITS FOR TESTING INTER-DEVICE FPGA LINKS INCLUDING A SHIFT REGISTER CONFIGURED FROM FPGA ELEMENTS TO FORM A SHIFT BLOCK THROUGH SAID INTER-DEVICE FPGA LINKS
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Patent #:
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|
Issue Dt:
|
07/03/2001
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Application #:
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09261776
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Filing Dt:
|
03/03/1999
|
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Title:
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FAULT TOLERANT OPERATION OF FIELD PROGRAMMABLE GATE ARRAYS
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|
|
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Patent #:
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|
Issue Dt:
|
04/15/2003
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Application #:
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09405958
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Filing Dt:
|
09/27/1999
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|
Title:
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ON-LINE TESTING OF THE PROGRAMMABLE LOGIC BLOCKS IN FIELD PROGRAMMABLE GATE ARRAYS
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|
|
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09406219
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Filing Dt:
|
09/27/1999
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|
Title:
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ON-LINE TESTING OF THE PROGRAMMABLE INTERCONNECT NETWORK IN FIELD PROGRAMMABLE GATE ARRAYS
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|
|
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Patent #:
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|
Issue Dt:
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10/24/2000
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Application #:
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09452017
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Filing Dt:
|
11/30/1999
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|
Title:
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METHOD FOR IN-SYSTEM PROGRAMMING OF SERIALLY CONFIGURED EEPROMS USING A JTAG INTERFACE OF A FIELD PROGRAMMABLE GATE ARRAY
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|
|
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Patent #:
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Issue Dt:
|
03/04/2003
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Application #:
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09611449
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Filing Dt:
|
07/06/2000
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Title:
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ON-LINE FAULT TOLERANT OPERATION VIA INCREMENTAL RECONFIGURATION OF FIELD PROGRAMMABLE GATE ARRAYS
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Patent #:
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Issue Dt:
|
12/17/2002
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Application #:
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09818257
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Filing Dt:
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03/27/2001
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|
Publication #:
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|
Pub Dt:
|
11/21/2002
| | | | |
|
Title:
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PROGRAMMING PROGRAMMABLE LOGIC DEVICES USING HIDDEN SWITCHES
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/18/2003
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Application #:
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09863656
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Filing Dt:
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05/23/2001
|
|
Publication #:
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Pub Dt:
|
12/27/2001
| | | | |
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Title:
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CLOCK SIGNAL SELECTION SYSTEM, METHOD OF GENERATING A CLOCK SIGNAL AND PROGRAMMABLE CLOCK MANAGER INCLUDING SAME
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