Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 037692/0902 | |
| Pages: | 6 |
| | Recorded: | 02/10/2016 | | |
Attorney Dkt #: | 13335/15147 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2018
|
Application #:
|
15019504
|
Filing Dt:
|
02/09/2016
|
Title:
|
METHOD AND APPARATUS FOR TESTING ERROR CORRECTION CODE (ECC) LOGIC AND PHYSICAL MEMORY ONBOARD A MANUFACTURED INTEGRATED CIRCUIT (IC)
|
|
Assignee
|
|
|
2655 SEELY AVENUE |
BUILDING 5 |
SAN JOSE, CALIFORNIA 95134 |
|
Correspondence name and address
|
|
CADENCE DESIGN SYSTEMS, INC. - KENYON
|
|
C/O KENYON & KENYON LLP
|
|
1801 PAGE MILL ROAD, SUITE 210
|
|
PALO ALTO, CA 94304-1216
|
Search Results as of:
09/21/2024 10:45 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|