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Patent Assignment Details

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Reel/Frame:	026144/0905			Pages:	5
		Recorded:	04/18/2011
Attorney Dkt #:	60961-28001.00
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 24

Patent #:	7714315	Issue Dt:	05/11/2010	Application #:	11437211	Filing Dt:	05/19/2006
Publication #:	US20070181932	Pub Dt:	08/09/2007
Title:	THERMAL ISOLATION OF PHASE CHANGE MEMORY CELLS

Patent #:	7626858	Issue Dt:	12/01/2009	Application #:	11450605	Filing Dt:	06/09/2006
Publication #:	US20070285976	Pub Dt:	12/13/2007
Title:	INTERGRATED CIRCUIT HAVING A PRECHARGING CIRCUIT

Patent #:	7376042	Issue Dt:	05/20/2008	Application #:	11492636	Filing Dt:	07/25/2006
Publication #:	US20080031057	Pub Dt:	02/07/2008
Title:	BOOSTED CLOCK CIRCUIT FOR SEMICONDUCTOR MEMORY

Patent #:	7541609	Issue Dt:	06/02/2009	Application #:	11601304	Filing Dt:	11/17/2006
Publication #:	US20080116442	Pub Dt:	05/22/2008
Title:	PHASE CHANGE MEMORY CELL HAVING A SIDEWALL CONTACT

Patent #:	7436695	Issue Dt:	10/14/2008	Application #:	11602720	Filing Dt:	11/21/2006
Publication #:	US20080117667	Pub Dt:	05/22/2008
Title:	RESISTIVE MEMORY INCLUDING BIPOLAR TRANSISTOR ACCESS DEVICES

Patent #:	7515461	Issue Dt:	04/07/2009	Application #:	11620432	Filing Dt:	01/05/2007
Publication #:	US20080165570	Pub Dt:	07/10/2008
Title:	CURRENT COMPLIANT SENSING ARCHITECTURE FOR MULTILEVEL PHASE CHANGE MEMORY

Patent #:	7652914	Issue Dt:	01/26/2010	Application #:	11651157	Filing Dt:	01/09/2007
Publication #:	US20080165573	Pub Dt:	07/10/2008
Title:	MEMORY INCLUDING TWO ACCESS DEVICES PER PHASE CHANGE ELEMENT

Patent #:	7525176	Issue Dt:	04/28/2009	Application #:	11668992	Filing Dt:	01/30/2007
Publication #:	US20080179591	Pub Dt:	07/31/2008
Title:	PHASE CHANGE MEMORY CELL DESIGN WITH ADJUSTED SEAM LOCATION

Patent #:	7626860	Issue Dt:	12/01/2009	Application #:	11690451	Filing Dt:	03/23/2007
Publication #:	US20080232158	Pub Dt:	09/25/2008
Title:	OPTIMIZED PHASE CHANGE WRITE METHOD

Patent #:	7564710	Issue Dt:	07/21/2009	Application #:	11742090	Filing Dt:	04/30/2007
Publication #:	US20080266932	Pub Dt:	10/30/2008
Title:	CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT

Patent #:	7671354	Issue Dt:	03/02/2010	Application #:	11760913	Filing Dt:	06/11/2007
Publication #:	US20080303013	Pub Dt:	12/11/2008
Title:	INTEGRATED CIRCUIT INCLUDING SPACER DEFINED ELECTRODE

Patent #:	8138028	Issue Dt:	03/20/2012	Application #:	11764678	Filing Dt:	06/18/2007
Publication #:	US20080191187	Pub Dt:	08/14/2008
Title:	METHOD FOR MANUFACTURING A PHASE CHANGE MEMORY DEVICE WITH PILLAR BOTTOM ELECTRODE

Patent #:	7906368	Issue Dt:	03/15/2011	Application #:	11771501	Filing Dt:	06/29/2007
Publication #:	US20090001341	Pub Dt:	01/01/2009
Title:	PHASE CHANGE MEMORY WITH TAPERED HEATER

Patent #:	7745807	Issue Dt:	06/29/2010	Application #:	11776301	Filing Dt:	07/11/2007
Publication #:	US20090014704	Pub Dt:	01/15/2009
Title:	CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE

Patent #:	7863610	Issue Dt:	01/04/2011	Application #:	11843044	Filing Dt:	08/22/2007
Publication #:	US20090052230	Pub Dt:	02/26/2009
Title:	INTEGRATED CIRCUIT INCLUDING SILICIDE REGION TO INHIBIT PARASITIC CURRENTS

Patent #:	7593255	Issue Dt:	09/22/2009	Application #:	11952462	Filing Dt:	12/07/2007
Publication #:	US20090147563	Pub Dt:	06/11/2009
Title:	INTEGRATED CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT

Patent #:	8189372	Issue Dt:	05/29/2012	Application #:	12025898	Filing Dt:	02/05/2008
Publication #:	US20090196094	Pub Dt:	08/06/2009
Title:	INTEGRATED CIRCUIT INCLUDING ELECTRODE HAVING RECESSED PORTION

Patent #:	7778070	Issue Dt:	08/17/2010	Application #:	12120946	Filing Dt:	05/15/2008
Publication #:	US20090003046	Pub Dt:	01/01/2009
Title:	MEMORY WITH DYNAMIC REDUNDANCY CONFIGURATION

Patent #:	8586960	Issue Dt:	11/19/2013	Application #:	12142239	Filing Dt:	06/19/2008
Publication #:	US20090316473	Pub Dt:	12/24/2009
Title:	INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE

Patent #:	NONE	Issue Dt:		Application #:	12177435	Filing Dt:	07/22/2008
Publication #:	US20100019215	Pub Dt:	01/28/2010
Title:	MUSHROOM TYPE MEMORY CELL HAVING SELF-ALIGNED BOTTOM ELECTRODE AND DIODE ACCESS DEVICE

Patent #:	8041865	Issue Dt:	10/18/2011	Application #:	12185472	Filing Dt:	08/04/2008
Publication #:	US20100030934	Pub Dt:	02/04/2010
Title:	BUS TERMINATION SYSTEM AND METHOD

Patent #:	7848153	Issue Dt:	12/07/2010	Application #:	12194414	Filing Dt:	08/19/2008
Publication #:	US20100046266	Pub Dt:	02/25/2010
Title:	HIGH SPEED MEMORY ARCHITECTURE

Patent #:	7771206	Issue Dt:	08/10/2010	Application #:	12209019	Filing Dt:	09/11/2008
Publication #:	US20100062621	Pub Dt:	03/11/2010
Title:	HORIZONTAL DUAL IN-LINE MEMORY MODULES

Patent #:	8161219	Issue Dt:	04/17/2012	Application #:	12328690	Filing Dt:	12/04/2008
Publication #:	US20100082871	Pub Dt:	04/01/2010
Title:	DISTRIBUTED COMMAND AND ADDRESS BUS ARCHITECTURE FOR A MEMORY MODULE HAVING PORTIONS OF BUS LINES SEPARATELY DISPOSED

Assignor

Exec Dt:

02/21/2011

Assignee

GUSTAV-HEINEMANN-RING 212

MUNICH, GERMANY 81379

Correspondence name and address
	BARRY E. BRETSCHNEIDER
	C/O MORRISON & FOERSTER LLP
	1650 TYSONS BLVD STE 400
	MCLEAN, VA 22102

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