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Reel/Frame:021901/0906   Pages: 4
Recorded: 12/02/2008
Attorney Dkt #:SPRINGSOFT
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 25
1
Patent #:
6321363
Issue Dt:
11/20/2001
Application #:
09228905
Filing Dt:
01/11/1999
Title:
INCREMENTAL SIMULATION USING PREVIOUS SIMULATION RESULTS AND KNOWLEDGE OF CHANGES TO SIMULATION MODEL TO ACHIEVE FAST SIMULATION TIME
2
Patent #:
6341366
Issue Dt:
01/22/2002
Application #:
09232467
Filing Dt:
01/15/1999
Title:
RULE-DRIVEN METHOD AND SYSTEM FOR EDITING PHYSICAL INTEGRATED CIRCUIT LAYOUTS
3
Patent #:
6366874
Issue Dt:
04/02/2002
Application #:
09317691
Filing Dt:
05/24/1999
Title:
SYSTEM AND METHOD FOR BROWSING GRAPHICALLY AN ELECTRONIC DESIGN BASED ON A HARDWARE DESCRIPTION LANGUAGE SPECIFICATION
4
Patent #:
6691079
Issue Dt:
02/10/2004
Application #:
09322185
Filing Dt:
05/28/1999
Title:
METHOD AND SYSTEM FOR ANALYZING TEST COVERAGE
5
Patent #:
6457163
Issue Dt:
09/24/2002
Application #:
09480063
Filing Dt:
01/10/2000
Title:
METHOD AND SYSTEM FOR CONSTRUCTING AND MANIPULATING A PHYSICAL INTEGRATED CIRCUIT LAYOUT OF A MULTIPLE-GATE SEMICONDUCTOR DEVICE
6
Patent #:
7013457
Issue Dt:
03/14/2006
Application #:
09682140
Filing Dt:
07/26/2001
Publication #:
US20040205717
Pub Dt:
10/14/2004
Title:
PRIORITIZED DEBUGGING OF AN ERROR SPACE IN PROGRAM CODE
7
Patent #:
6546526
Issue Dt:
04/08/2003
Application #:
09764396
Filing Dt:
01/19/2001
Publication #:
US20020100001
Pub Dt:
07/25/2002
Title:
ACTIVE TRACE DEBUGGING FOR HARDWARE DESCRIPTION LANGUAGES
8
Patent #:
6980211
Issue Dt:
12/27/2005
Application #:
10064035
Filing Dt:
06/04/2002
Publication #:
US20030222872
Pub Dt:
12/04/2003
Title:
AUTOMATIC SCHEMATIC DIAGRAM GENERATION USING TOPOLOGY INFORMATION
9
Patent #:
6751565
Issue Dt:
06/15/2004
Application #:
10064213
Filing Dt:
06/21/2002
Publication #:
US20030236640
Pub Dt:
12/25/2003
Title:
FAST WAVEFORM DISPLAY METHOD AND SYSTEM
10
Patent #:
6920620
Issue Dt:
07/19/2005
Application #:
10160690
Filing Dt:
05/31/2002
Publication #:
US20030135831
Pub Dt:
07/17/2003
Title:
METHOD AND SYSTEM FOR CREATING TEST COMPONENT LAYOUTS
11
Patent #:
7283944
Issue Dt:
10/16/2007
Application #:
10737154
Filing Dt:
12/15/2003
Publication #:
US20050131666
Pub Dt:
06/16/2005
Title:
CIRCUIT SIMULATION BUS TRANSACTION ANALYSIS
12
Patent #:
7178114
Issue Dt:
02/13/2007
Application #:
10863122
Filing Dt:
06/07/2004
Publication #:
US20040225986
Pub Dt:
11/11/2004
Title:
SCRIPTED, HIERARCHICAL TEMPLATE-BASED IC PHYSICAL LAYOUT SYSTEM
13
Patent #:
7178123
Issue Dt:
02/13/2007
Application #:
10975151
Filing Dt:
10/27/2004
Publication #:
US20060090152
Pub Dt:
04/27/2006
Title:
SCHEMATIC DIAGRAM GENERATION AND DISPLAY SYSTEM
14
Patent #:
7257794
Issue Dt:
08/14/2007
Application #:
11039751
Filing Dt:
01/19/2005
Publication #:
US20060136856
Pub Dt:
06/22/2006
Title:
UNIT-BASED LAYOUT SYSTEM FOR PASSIVE IC DEVICES
15
Patent #:
7310786
Issue Dt:
12/18/2007
Application #:
11051074
Filing Dt:
02/03/2005
Publication #:
US20060190847
Pub Dt:
08/24/2006
Title:
IC COMPACTION SYSTEM
16
Patent #:
7386823
Issue Dt:
06/10/2008
Application #:
11186165
Filing Dt:
07/20/2005
Publication #:
US20070022399
Pub Dt:
01/25/2007
Title:
RULE-BASED SCHEMATIC DIAGRAM GENERATOR
17
Patent #:
7461310
Issue Dt:
12/02/2008
Application #:
11450941
Filing Dt:
06/08/2006
Publication #:
US20070288818
Pub Dt:
12/13/2007
Title:
IC FUNCTIONAL AND DELAY FAULT TESTING
18
Patent #:
8479132
Issue Dt:
07/02/2013
Application #:
11455134
Filing Dt:
06/16/2006
Publication #:
US20070294651
Pub Dt:
12/20/2007
Title:
Active trace assertion based verification system
19
Patent #:
NONE
Issue Dt:
Application #:
11470312
Filing Dt:
09/06/2006
Publication #:
US20080082880
Pub Dt:
04/03/2008
Title:
METHOD OF TESTING HIGH-SPEED IC WITH LOW-SPEED IC TESTER
20
Patent #:
7603640
Issue Dt:
10/13/2009
Application #:
11550487
Filing Dt:
10/18/2006
Publication #:
US20080155485
Pub Dt:
06/26/2008
Title:
MULTILEVEL IC FLOORPLANNER
21
Patent #:
7707536
Issue Dt:
04/27/2010
Application #:
11681859
Filing Dt:
03/05/2007
Publication #:
US20070256045
Pub Dt:
11/01/2007
Title:
V-SHAPED MULTILEVEL FULL-CHIP GRIDLESS ROUTING
22
Patent #:
7779379
Issue Dt:
08/17/2010
Application #:
11761166
Filing Dt:
06/11/2007
Publication #:
US20070288878
Pub Dt:
12/13/2007
Title:
TEMPLATE-BASED GATEWAY MODEL ROUTING SYSTEM
23
Patent #:
7739646
Issue Dt:
06/15/2010
Application #:
11839042
Filing Dt:
08/15/2007
Publication #:
US20080092099
Pub Dt:
04/17/2008
Title:
ANALOG AND MIXED SIGNAL IC LAYOUT SYSTEM
24
Patent #:
7877718
Issue Dt:
01/25/2011
Application #:
11930992
Filing Dt:
10/31/2007
Publication #:
US20090113367
Pub Dt:
04/30/2009
Title:
ANALOG IC PLACEMENT USING SYMMETRY-ISLANDS
25
Patent #:
7984410
Issue Dt:
07/19/2011
Application #:
12168288
Filing Dt:
07/07/2008
Publication #:
US20090031269
Pub Dt:
01/29/2009
Title:
A HIERARCHY-BASED ANALYTICAL PLACEMENT METHOD FOR AN INTEGRATED CIRCUIT
Assignor
1
SPRINGSOFT, INC.
Exec Dt:
12/01/2008
Assignee
1
SPRINGSOFT USA, INC.
2025 GATEWAY PLACE, SUITE 400
SAN JOSE, CALIFORNIA 95110
Correspondence name and address
PENNY STOCKWELL
16100 NW CORNELL ROAD, SUITE 220
BEAVERTON, OR 97006

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