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Reel/Frame:	025105/0907			Pages:	57
		Recorded:	10/08/2010
Attorney Dkt #:	22524-00230
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 264
Page 3 of 3
Pages: 1 2 3

1

Patent #:	7573749	Issue Dt:	08/11/2009	Application #:	11731228	Filing Dt:	03/29/2007
Publication #:	US20070171724	Pub Dt:	07/26/2007
Title:	COUNTERACTING OVERTUNNELING IN NONVOLATILE MEMORY CELLS

2

Patent #:	7673264	Issue Dt:	03/02/2010	Application #:	11732900	Filing Dt:	04/05/2007
Title:	SYSTEM AND METHOD FOR VERIFYING IP INTEGRITY IN SYSTEM-ON-CHIP (SOC) DESIGN

3

Patent #:	8132142	Issue Dt:	03/06/2012	Application #:	11734202	Filing Dt:	04/11/2007
Publication #:	US20070180419	Pub Dt:	08/02/2007
Title:	VARIOUS METHODS AND APPARATUSES TO ROUTE MULTIPLE POWER RAILS TO A CELL

4

Patent #:	7791950	Issue Dt:	09/07/2010	Application #:	11748541	Filing Dt:	05/15/2007
Publication #:	US20070263456	Pub Dt:	11/15/2007
Title:	INVERTER NON-VOLATILE MEMORY CELL AND ARRAY SYSTEM

5

Patent #:	7898882	Issue Dt:	03/01/2011	Application #:	11766943	Filing Dt:	06/22/2007
Publication #:	US20080008015	Pub Dt:	01/10/2008
Title:	ARCHITECTURE, SYSTEM AND METHOD FOR COMPRESSING REPAIR DATA IN AN INTEGRATED CIRCUIT (IC) DESIGN

6

Patent #:	8122307	Issue Dt:	02/21/2012	Application #:	11768974	Filing Dt:	06/27/2007
Title:	ONE TIME PROGRAMMABLE MEMORY TEST STRUCTURES AND METHODS

7

Patent #:	8429375	Issue Dt:	04/23/2013	Application #:	11818757	Filing Dt:	06/15/2007
Title:	MEMORY MANAGEMENT UNIT (MMU) TO MAKE ONLY ONE TIME PROGRAMMABLE (OTP) MEMORY APPEAR MULTIPLE TIMES PROGRAMMABLE (MTP)

8

Patent #:	8077511	Issue Dt:	12/13/2011	Application #:	11829370	Filing Dt:	07/27/2007
Publication #:	US20080205150	Pub Dt:	08/28/2008
Title:	HYBRID NON-VOLATILE MEMORY

9

Patent #:	8022498	Issue Dt:	09/20/2011	Application #:	11837810	Filing Dt:	08/13/2007
Title:	ELECTROSTATIC DISCHARGE MANAGEMENT APPARATUS, SYSTEMS, AND METHODS

10

Patent #:	7843316	Issue Dt:	11/30/2010	Application #:	11842862	Filing Dt:	08/21/2007
Title:	POWER-ON RESET APPARATUS, SYSTEMS, AND METHODS

11

Patent #:	7768840	Issue Dt:	08/03/2010	Application #:	11847047	Filing Dt:	08/29/2007
Title:	MEMORY MODELING USING AN INTERMEDIATE LEVEL STRUCTURAL DESCRIPTION

12

Patent #:	8111558	Issue Dt:	02/07/2012	Application #:	11865777	Filing Dt:	10/02/2007
Publication #:	US20080175050	Pub Dt:	07/24/2008
Title:	PFET NONVOLATILE MEMORY

13

Patent #:	7989849	Issue Dt:	08/02/2011	Application #:	11870330	Filing Dt:	10/10/2007
Publication #:	US20080111158	Pub Dt:	05/15/2008
Title:	APPARATUSES AND METHODS FOR EFFICIENT POWER RAIL STRUCTURES FOR CELL LIBRARIES

14

Patent #:	8166450	Issue Dt:	04/24/2012	Application #:	11906519	Filing Dt:	10/01/2007
Publication #:	US20080320246	Pub Dt:	12/25/2008
Title:	METHODS AND APPARATUS FOR COMPILING INSTRUCTIONS FOR A DATA PROCESSOR

15

Patent #:	7904766	Issue Dt:	03/08/2011	Application #:	11951338	Filing Dt:	12/06/2007
Title:	STATISTICAL YIELD OF A SYSTEM-ON-A-CHIP

16

Patent #:	7843032	Issue Dt:	11/30/2010	Application #:	11965307	Filing Dt:	12/27/2007
Title:	RADIO FREQUENCY IDENTIFICATION DEVICE ELECTROSTATIC DISCHARGE MANAGEMENT

17

Patent #:	7872566	Issue Dt:	01/18/2011	Application #:	11965359	Filing Dt:	12/27/2007
Title:	RADIO FREQUENCY IDENTIFICATION DEVICE POWER-ON RESET MANAGEMENT

18

Patent #:	7760575	Issue Dt:	07/20/2010	Application #:	11968021	Filing Dt:	12/31/2007
Publication #:	US20090168497	Pub Dt:	07/02/2009
Title:	MEMORY LEAKAGE CONTROL CIRCUIT AND METHOD

19

Patent #:	8006069	Issue Dt:	08/23/2011	Application #:	11973173	Filing Dt:	10/05/2007
Publication #:	US20080086626	Pub Dt:	04/10/2008
Title:	INTER-PROCESSOR COMMUNICATION METHOD

20

Patent #:	7719896	Issue Dt:	05/18/2010	Application #:	11981056	Filing Dt:	10/30/2007
Title:	CONFIGURABLE SINGLE BIT/DUAL BITS MEMORY

21

Patent #:	7724570	Issue Dt:	05/25/2010	Application #:	11982277	Filing Dt:	10/31/2007
Title:	ADAPTIVE PROGRAMMING OF MEMORY CIRCUIT INCLUDING WRITING DATA IN CELLS OF A MEMORY CIRCUIT

22

Patent #:	7724571	Issue Dt:	05/25/2010	Application #:	11982278	Filing Dt:	10/31/2007
Title:	METHODS FOR ADAPTIVE PROGRAMMING OF MEMORY CIRCUIT INCLUDING WRITING DATA IN CELLS OF A MEMORY CIRCUIT

23

Patent #:	8433879	Issue Dt:	04/30/2013	Application #:	12006321	Filing Dt:	12/31/2007
Title:	RFID tag semiconductor chip with memory management unit (MMU) to make only one time programmable (OTP) memory appear multiple times programmable (MTP)

24

Patent #:	8373167	Issue Dt:	02/12/2013	Application #:	12006330	Filing Dt:	12/31/2007
Publication #:	US20080185627	Pub Dt:	08/07/2008
Title:	RFID TAG HAVING NON-VOLATILE MEMORY DEVICE HAVING FLOATING-GATE FETS WITH DIFFERENT SOURCE-GATE AND DRAIN-GATE BORDER LENGTHS

25

Patent #:	7796450	Issue Dt:	09/14/2010	Application #:	12012910	Filing Dt:	02/05/2008
Title:	RADIO FREQUENCY (RFID) TAG INCLUDING CONFIGURABLE SINGLE BIT/DUAL BITS MEMORY

26

Patent #:	7808823	Issue Dt:	10/05/2010	Application #:	12020522	Filing Dt:	01/26/2008
Publication #:	US20080136602	Pub Dt:	06/12/2008
Title:	RFID TAG WITH REDUNDANT NON-VOLATILE MEMORY CELL

27

Patent #:	8179171	Issue Dt:	05/15/2012	Application #:	12057355	Filing Dt:	03/27/2008
Title:	POWER UP CIRCUIT

28

Patent #:	7652921	Issue Dt:	01/26/2010	Application #:	12080127	Filing Dt:	03/31/2008
Publication #:	US20080279013	Pub Dt:	11/13/2008
Title:	MULTI-LEVEL NON-VOLATILE MEMORY CELL WITH HIGH-VT ENHANCED BTBT DEVICE

29

Patent #:	7609550	Issue Dt:	10/27/2009	Application #:	12099640	Filing Dt:	04/08/2008
Publication #:	US20080212355	Pub Dt:	09/04/2008
Title:	COMPACT VIRTUAL GROUND DIFFUSION PROGRAMMABLE ROM ARRAY ARCHITECTURE, SYSTEM AND METHOD

30

Patent #:	7920423	Issue Dt:	04/05/2011	Application #:	12114574	Filing Dt:	05/02/2008
Title:	NON VOLATILE MEMORY CIRCUIT WITH TAILORED RELIABILITY

31

Patent #:	8004310	Issue Dt:	08/23/2011	Application #:	12125063	Filing Dt:	05/22/2008
Title:	POWER SUPPLY REGULATION

32

Patent #:	8098088	Issue Dt:	01/17/2012	Application #:	12143133	Filing Dt:	06/20/2008
Title:	HIGH-VOLTAGE SWITCH USING THREE FETS

33

Patent #:	8201064	Issue Dt:	06/12/2012	Application #:	12143250	Filing Dt:	06/20/2008
Publication #:	US20090077451	Pub Dt:	03/19/2009
Title:	METHOD AND APPARATUS FOR IMPLEMENTING DECODE OPERATIONS IN A DATA PROCESSOR

34

Patent #:	8688879	Issue Dt:	04/01/2014	Application #:	12143351	Filing Dt:	06/20/2008
Publication #:	US20090055565	Pub Dt:	02/26/2009
Title:	MEMORY INTERFACE AND METHOD OF INTERFACING BETWEEN FUNCTIONAL ENTITIES

35

Patent #:	8879636	Issue Dt:	11/04/2014	Application #:	12154783	Filing Dt:	05/27/2008
Publication #:	US20080291995	Pub Dt:	11/27/2008
Title:	ADAPTIVE VIDEO ENCODING APPARATUS AND METHODS

36

Patent #:	7788551	Issue Dt:	08/31/2010	Application #:	12188892	Filing Dt:	08/08/2008
Publication #:	US20080301507	Pub Dt:	12/04/2008
Title:	SYSTEM AND METHOD FOR REPAIRING A MEMORY

37

Patent #:	7890900	Issue Dt:	02/15/2011	Application #:	12194454	Filing Dt:	08/19/2008
Publication #:	US20100050135	Pub Dt:	02/25/2010
Title:	VARIOUS METHODS AND APPARATUSES FOR EFFECTIVE YIELD ENHANCEMENT OF GOOD CHIP DIES HAVING MEMORIES PER WAFER

38

Patent #:	7894261	Issue Dt:	02/22/2011	Application #:	12239696	Filing Dt:	09/26/2008
Title:	PFET NONVOLATILE MEMORY

39

Patent #:	8112730	Issue Dt:	02/07/2012	Application #:	12249085	Filing Dt:	10/10/2008
Publication #:	US20090106716	Pub Dt:	04/23/2009
Title:	VARIOUS METHODS AND APPARATUSES FOR MEMORY MODELING USING A STRUCTURAL PRIMITIVE VERIFICATION FOR MEMORY COMPILERS

40

Patent #:	8063623	Issue Dt:	11/22/2011	Application #:	12299305	Filing Dt:	10/31/2008
Publication #:	US20090315532	Pub Dt:	12/24/2009
Title:	VERY LOW POWER ANALOG COMPENSATION CIRCUIT

41

Patent #:	8106705	Issue Dt:	01/31/2012	Application #:	12299726	Filing Dt:	11/05/2008
Publication #:	US20090189649	Pub Dt:	07/30/2009
Title:	CONTROL CIRCUIT FOR PVT CONDITIONS OF A MODULE

42

Patent #:	8325618	Issue Dt:	12/04/2012	Application #:	12307411	Filing Dt:	07/02/2009
Publication #:	US20100002589	Pub Dt:	01/07/2010
Title:	ELECTRONIC DEVICE, SYTEM ON CHIP AND METHOD FOR MONITORING A DATA FLOW

43

Patent #:	7911873	Issue Dt:	03/22/2011	Application #:	12346854	Filing Dt:	12/31/2008
Title:	DIGITAL DELAY LOCKED LOOP IMPLEMENTATION FOR PRECISE CONTROL OF TIMING SIGNALS

44

Patent #:	8452920	Issue Dt:	05/28/2013	Application #:	12346856	Filing Dt:	12/31/2008
Title:	SYSTEM AND METHOD FOR CONTROLLING A DYNAMIC RANDOM ACCESS MEMORY

45

Patent #:	8601205	Issue Dt:	12/03/2013	Application #:	12346859	Filing Dt:	12/31/2008
Title:	DYNAMIC RANDOM ACCESS MEMORY CONTROLLER

46

Patent #:	8484411	Issue Dt:	07/09/2013	Application #:	12346860	Filing Dt:	12/31/2008
Title:	SYSTEM AND METHOD FOR IMPROVING ACCESS EFFICIENCY TO A DYNAMIC RANDOM ACCESS MEMORY

47

Patent #:	8031541	Issue Dt:	10/04/2011	Application #:	12346862	Filing Dt:	12/31/2008
Title:	LOW LEAKAGE ROM ARCHITECTURE

48

Patent #:	8546251	Issue Dt:	10/01/2013	Application #:	12346866	Filing Dt:	12/31/2008
Title:	COMPACT READ ONLY MEMORY CELL

49

Patent #:	8065542	Issue Dt:	11/22/2011	Application #:	12347008	Filing Dt:	12/31/2008
Publication #:	US20100169680	Pub Dt:	07/01/2010
Title:	DISTRIBUTED TABLE-DRIVEN POWER MODE COMPUTATION FOR CONTROLLING OPTIMAL CLOCK AND VOLTAGE SWITCHING

50

Patent #:	7718492	Issue Dt:	05/18/2010	Application #:	12403333	Filing Dt:	03/12/2009
Publication #:	US20090170260	Pub Dt:	07/02/2009
Title:	NON-VOLATILE MEMORY CELL CIRCUIT WITH PROGRAMMING THROUGH BAND-TO-BAND TUNNELING AND IMPACT IONIZATION GATE CURRENT

51

Patent #:	7983093	Issue Dt:	07/19/2011	Application #:	12410417	Filing Dt:	03/24/2009
Publication #:	US20090238008	Pub Dt:	09/24/2009
Title:	NON-VOLATILE MEMORY CELL WITH BTBT PROGRAMMING

52

Patent #:	8330491	Issue Dt:	12/11/2012	Application #:	12532201	Filing Dt:	09/21/2009
Publication #:	US20100085080	Pub Dt:	04/08/2010
Title:	ELECTRONIC DEVICE WITH A HIGH VOLTAGE TOLERANT UNIT

53

Patent #:	7940550	Issue Dt:	05/10/2011	Application #:	12558816	Filing Dt:	09/14/2009
Publication #:	US20110063893	Pub Dt:	03/17/2011
Title:	SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPACITY MEMORIES BY SELECTIVE BIASING

54

Patent #:	7929347	Issue Dt:	04/19/2011	Application #:	12577405	Filing Dt:	10/12/2009
Publication #:	US20100027312	Pub Dt:	02/04/2010
Title:	COMPACT VIRTUAL GROUND DIFFUSION PROGRAMMABLE ROM ARRAY ARCHITECTURE, SYSTEM AND METHOD

55

Patent #:	8386972	Issue Dt:	02/26/2013	Application #:	12639911	Filing Dt:	12/16/2009
Publication #:	US20100299647	Pub Dt:	11/25/2010
Title:	METHOD AND APPARATUS FOR MANAGING THE CONFIGURATION AND FUNCTIONALITY OF A SEMICONDUCTOR DESIGN

56

Patent #:	8327309	Issue Dt:	12/04/2012	Application #:	12673445	Filing Dt:	01/26/2011
Publication #:	US20110239067	Pub Dt:	09/29/2011
Title:	VERIFICATION OF DESIGN INFORMATION FOR CONTROLLING MANUFACTURE OF A SYSTEM ON A CHIP

57

Patent #:	8193835	Issue Dt:	06/05/2012	Application #:	12716287	Filing Dt:	03/03/2010
Title:	A CIRCUIT AND METHOD FOR SWITCHING VOLTAGE

58

Patent #:	8501562	Issue Dt:	08/06/2013	Application #:	12717966	Filing Dt:	03/05/2010
Title:	FABRICATING A GATE OXIDE

59

Patent #:	8667319	Issue Dt:	03/04/2014	Application #:	12741001	Filing Dt:	09/02/2010
Publication #:	US20100327938	Pub Dt:	12/30/2010
Title:	SYSTEM AND METHOD FOR CLOCK CONTROL FOR POWER-STATE TRANSITIONS

60

Patent #:	7969191	Issue Dt:	06/28/2011	Application #:	12866734	Filing Dt:	09/24/2010
Publication #:	US20110006810	Pub Dt:	01/13/2011
Title:	LOW-SWING CMOS INPUT CIRCUIT

61

Patent #:	8294504	Issue Dt:	10/23/2012	Application #:	12919077	Filing Dt:	10/25/2010
Publication #:	US20110050313	Pub Dt:	03/03/2011
Title:	METHODS AND SYSTEMS RELATED TO A CONFIGURABLE DELAY COUNTER USED WITH VARIABLE FREQUENCY CLOCKS

62

Patent #:	8533517	Issue Dt:	09/10/2013	Application #:	12919099	Filing Dt:	10/18/2010
Publication #:	US20110026656	Pub Dt:	02/03/2011
Title:	CLOCK SWITCHING CIRCUITS AND METHODS TO SELECT FROM MULTIPLE CLOCK SOURCES

63

Patent #:	8466723	Issue Dt:	06/18/2013	Application #:	12919186	Filing Dt:	11/17/2010
Publication #:	US20110050300	Pub Dt:	03/03/2011
Title:	CLOCK GENERATOR

64

Patent #:	8838863	Issue Dt:	09/16/2014	Application #:	12919864	Filing Dt:	11/17/2010
Publication #:	US20110055444	Pub Dt:	03/03/2011
Title:	Resource Controlling With Dynamic Priority Adjustment

Assignors

1

VIRAGE LOGIC CORPORATION

Exec Dt:

09/02/2010

2

Exec Dt:

09/02/2010

3

ARC CORES LIMITED

Exec Dt:

09/02/2010

4

ARC INTERNATIONAL I.P., INC.

Exec Dt:

09/02/2010

5

ARC INTERNATIONAL INTELLECTUAL PROPERTY, INC.

Exec Dt:

09/02/2010

6

ARC INTERNATIONAL LIMITED, FORMERLY ARC INTERNATIONAL PLC

Exec Dt:

09/02/2010

7

ARC INTERNATIONAL (UK) LIMITED

Exec Dt:

09/02/2010

Assignee

1

700 EAST MIDDLEFIELD ROAD

MOUNTAIN VIEW, CALIFORNIA 94043

Correspondence name and address
	FENWICK & WEST LLP
	801 CALIFORNIA ST
	ATTN MICHAEL W. FARN
	MOUNTAIN VIEW, CA 94041

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