Total properties:
193
Page
2
of
2
Pages:
1 2 |
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2019
|
Application #:
|
15450893
|
Filing Dt:
|
03/06/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/22/2017
| | | | |
|
Title:
|
MEMORY HAVING A CONTINUOUS CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2020
|
Application #:
|
15451022
|
Filing Dt:
|
03/06/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/22/2017
| | | | |
|
Title:
|
REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15451090
|
Filing Dt:
|
03/06/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/06/2018
| | | | |
|
Title:
|
Integrated Structures, Capacitors and Methods of Forming Capacitors
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2018
|
Application #:
|
15452467
|
Filing Dt:
|
03/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2018
| | | | |
|
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING LINEAR STRUCTURES SUBSTANTIALLY ALIGNED WITH OTHER STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2018
|
Application #:
|
15452537
|
Filing Dt:
|
03/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/22/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR CHARGING A GLOBAL ACCESS LINE PRIOR TO ACCESSING A MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2019
|
Application #:
|
15454975
|
Filing Dt:
|
03/09/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/22/2017
| | | | |
|
Title:
|
METHODS AND APPARATUSES FOR COMPENSATING FOR SOURCE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2017
|
Application #:
|
15455859
|
Filing Dt:
|
03/10/2017
|
|
Title:
|
Conductive Components and Memory Assemblies
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2018
|
Application #:
|
15456164
|
Filing Dt:
|
03/10/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2017
| | | | |
|
Title:
|
MEMORY DEVICE COMMAND RECEIVING AND DECODING METHODS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15456175
|
Filing Dt:
|
03/10/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2018
| | | | |
|
Title:
|
METHODS FOR MITIGATING POWER LOSS EVENTS DURING OPERATION OF MEMORY DEVICES AND MEMORY DEVICES EMPLOYING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2019
|
Application #:
|
15456254
|
Filing Dt:
|
03/10/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2018
| | | | |
|
Title:
|
Assemblies Having Shield Lines of an Upper Wiring Layer Electrically Coupled with Shield Lines of a Lower Wiring Layer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
15457339
|
Filing Dt:
|
03/13/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2017
| | | | |
|
Title:
|
DATA SHIFT BY ELEMENTS OF A VECTOR IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2020
|
Application #:
|
15457473
|
Filing Dt:
|
03/13/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/31/2017
| | | | |
|
Title:
|
MEMORY ARRAY HAVING CONNECTIONS GOING THROUGH CONTROL GATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2020
|
Application #:
|
15458516
|
Filing Dt:
|
03/14/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/14/2017
| | | | |
|
Title:
|
FOLDING DEVICE STAND FOR PORTABLE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2018
|
Application #:
|
15458572
|
Filing Dt:
|
03/14/2017
|
|
Title:
|
Memory Cells and Integrated Structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2018
|
Application #:
|
15459136
|
Filing Dt:
|
03/15/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2017
| | | | |
|
Title:
|
METHODS OF FORMING A FERROELECTRIC MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2018
|
Application #:
|
15460206
|
Filing Dt:
|
03/15/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2017
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15460296
|
Filing Dt:
|
03/16/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/13/2017
| | | | |
|
Title:
|
SOLID STATE MEMORY FORMATTING WITH PADDING BETWEEN PORTIONS OF SYSTEM DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2019
|
Application #:
|
15461623
|
Filing Dt:
|
03/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/20/2018
| | | | |
|
Title:
|
ERROR CORRECTION CODE (ECC) OPERATIONS IN MEMORY FOR PROVIDING REDUNDANT ERROR CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2019
|
Application #:
|
15461672
|
Filing Dt:
|
03/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/20/2018
| | | | |
|
Title:
|
TIERED ERROR CORRECTION CODE (ECC) OPERATIONS IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15462618
|
Filing Dt:
|
03/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/07/2017
| | | | |
|
Title:
|
METHODS FOR FORMING NARROW VERTICAL PILLARS AND INTEGRATED CIRCUIT DEVICES HAVING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2018
|
Application #:
|
15463504
|
Filing Dt:
|
03/20/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/06/2017
| | | | |
|
Title:
|
MEMORY TILE ACCESS AND SELECTION PATTERNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2018
|
Application #:
|
15464012
|
Filing Dt:
|
03/20/2017
|
|
Title:
|
APPARATUSES AND METHODS FOR PARTIAL BIT DE-EMPHASIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2019
|
Application #:
|
15464060
|
Filing Dt:
|
03/20/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/06/2017
| | | | |
|
Title:
|
SEMICONDUCTOR-METAL-ON-INSULATOR STRUCTURES, METHODS OF FORMING SUCH STRUCTURES, AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2021
|
Application #:
|
15464596
|
Filing Dt:
|
03/21/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/06/2017
| | | | |
|
Title:
|
PACKAGED LEDS WITH PHOSPHOR FILMS, AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2018
|
Application #:
|
15464907
|
Filing Dt:
|
03/21/2017
|
|
Title:
|
TIMING CONTROL FOR INPUT RECEIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2020
|
Application #:
|
15465340
|
Filing Dt:
|
03/21/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2018
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR IN-MEMORY DATA SWITCHING NETWORKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15465421
|
Filing Dt:
|
03/21/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2018
| | | | |
|
Title:
|
METHODS AND APPARATUSES FOR SIGNAL TRANSLATION IN A BUFFERED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2018
|
Application #:
|
15465936
|
Filing Dt:
|
03/22/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/06/2017
| | | | |
|
Title:
|
TRANSISTORS HAVING STRAINED CHANNEL UNDER GATE IN A RECESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2022
|
Application #:
|
15466296
|
Filing Dt:
|
03/22/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2018
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR OPERATING NEURAL NETWORKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2019
|
Application #:
|
15466477
|
Filing Dt:
|
03/22/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2018
| | | | |
|
Title:
|
APPARATUS AND METHODS FOR IN DATA PATH COMPUTE OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15466689
|
Filing Dt:
|
03/22/2017
|
|
Title:
|
CHALCOGENIDE MEMORY DEVICE COMPONENTS AND COMPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2018
|
Application #:
|
15467765
|
Filing Dt:
|
03/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/06/2017
| | | | |
|
Title:
|
Vertical Memory Strings, and Vertically-Stacked Structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2017
|
Application #:
|
15468225
|
Filing Dt:
|
03/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/13/2017
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICES WITH MAGNETIC REGIONS AND ATTRACTER MATERIAL AND METHODS OF FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2018
|
Application #:
|
15468742
|
Filing Dt:
|
03/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2018
| | | | |
|
Title:
|
SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
15469287
|
Filing Dt:
|
03/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2018
| | | | |
|
Title:
|
MEMORY PROTECTION BASED ON SYSTEM STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2019
|
Application #:
|
15469865
|
Filing Dt:
|
03/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2018
| | | | |
|
Title:
|
MULTIPLE PLATE LINE ARCHITECTURE FOR MULTIDECK MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2018
|
Application #:
|
15470492
|
Filing Dt:
|
03/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/13/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR CURRENT LIMITATION IN THRESHOLD SWITCHING MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
15470516
|
Filing Dt:
|
03/27/2017
|
|
Title:
|
APPARATUSES AND METHODS FOR IN-MEMORY OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2020
|
Application #:
|
15470590
|
Filing Dt:
|
03/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/13/2017
| | | | |
|
Title:
|
CHAINED BUS MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2020
|
Application #:
|
15470617
|
Filing Dt:
|
03/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/13/2017
| | | | |
|
Title:
|
DEVICES AND METHODS INCLUDING AN ETCH STOP PROTECTION MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
15470698
|
Filing Dt:
|
03/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/13/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR CONFIGURING I/OS OF MEMORY FOR HYBRID MEMORY MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
15471420
|
Filing Dt:
|
03/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/13/2017
| | | | |
|
Title:
|
FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
15472052
|
Filing Dt:
|
03/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/13/2017
| | | | |
|
Title:
|
Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2019
|
Application #:
|
15472184
|
Filing Dt:
|
03/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2018
| | | | |
|
Title:
|
METHOD OF FORMING VIAS USING SILICON ON INSULATOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
|
Application #:
|
15472957
|
Filing Dt:
|
03/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2018
| | | | |
|
Title:
|
SELECTIVE ERROR RATE INFORMATION FOR MULTIDIMENSIONAL MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2018
|
Application #:
|
15473338
|
Filing Dt:
|
03/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/21/2017
| | | | |
|
Title:
|
STRUCTURES INCORPORATING AND METHODS OF FORMING METAL LINES INCLUDING CARBON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2018
|
Application #:
|
15474353
|
Filing Dt:
|
03/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
|
Title:
|
APPARATUSES, CIRCUITS, AND METHODS FOR BIASING SIGNAL LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2018
|
Application #:
|
15474786
|
Filing Dt:
|
03/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
|
Title:
|
ULTRATHIN SOLID STATE DIES AND METHODS OF MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2018
|
Application #:
|
15474854
|
Filing Dt:
|
03/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
|
Title:
|
MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2020
|
Application #:
|
15477169
|
Filing Dt:
|
04/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
|
Title:
|
RECOVERY FOR NON-VOLATILE MEMORY AFTER POWER LOSS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2018
|
Application #:
|
15478133
|
Filing Dt:
|
04/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
|
Title:
|
METHODS FOR FORMING INTERCONNECT ASSEMBLIES WITH PROBED BOND PADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
15478312
|
Filing Dt:
|
04/04/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
|
Title:
|
MEMORY DEVICES THAT APPLY A PROGRAMMING POTENTIAL TO A MEMORY CELL IN A STRING COUPLED TO A SOURCE AND DATA LINE CONCURRENTLY WITH BIASING THE DATA LINE TO A GREATER POTENTIAL THAN THE SOURCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2019
|
Application #:
|
15478631
|
Filing Dt:
|
04/04/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2018
| | | | |
|
Title:
|
GARBAGE COLLECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2019
|
Application #:
|
15479356
|
Filing Dt:
|
04/05/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2018
| | | | |
|
Title:
|
OPERATION OF MIXED MODE BLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15479403
|
Filing Dt:
|
04/05/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
|
Title:
|
MEMORY CELL WITH INDEPENDENTLY-SIZED ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2018
|
Application #:
|
15479520
|
Filing Dt:
|
04/05/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
|
Title:
|
FUNCTIONAL DATA PROGRAMMING IN A NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
15481208
|
Filing Dt:
|
04/06/2017
|
|
Publication #:
|
|
Pub Dt:
|
09/14/2017
| | | | |
|
Title:
|
REPLACEMENT MATERIALS PROCESSES FOR FORMING CROSS POINT MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2018
|
Application #:
|
15481301
|
Filing Dt:
|
04/06/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/27/2017
| | | | |
|
Title:
|
Semiconductor Devices Including a Diode Structure Over a Conductive Strap and Methods of Forming Such Semiconductor Devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2019
|
Application #:
|
15481331
|
Filing Dt:
|
04/06/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2018
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE ASSEMBLIES WITH MOLDED SUPPORT SUBSTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2018
|
Application #:
|
15482016
|
Filing Dt:
|
04/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2018
| | | | |
|
Title:
|
THREE DIMENSIONAL MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2018
|
Application #:
|
15482020
|
Filing Dt:
|
04/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2018
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR REDUCING IMPACT OF TRANSISTOR RANDOM MISMATCH IN CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2019
|
Application #:
|
15482263
|
Filing Dt:
|
04/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2018
| | | | |
|
Title:
|
METHODS OF BIT-FLAGGED SKETCH-BASED MEMORY MANAGEMENT AND MEMORY DEVICES UTILIZING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2019
|
Application #:
|
15482288
|
Filing Dt:
|
04/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2018
| | | | |
|
Title:
|
METHODS OF SKETCH-BASED MEMORY MANAGEMENT AND MEMORY DEVICES UTILIZING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2019
|
Application #:
|
15482337
|
Filing Dt:
|
04/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2018
| | | | |
|
Title:
|
MEMORY MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2020
|
Application #:
|
15483804
|
Filing Dt:
|
04/10/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/27/2017
| | | | |
|
Title:
|
MEMORY SYSTEMS AND METHODS INCLUDING TRAINING, DATA ORGANIZING, AND/OR SHADOWING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15484369
|
Filing Dt:
|
04/11/2017
|
|
Title:
|
METHODS AND APPARATUS HAVING MULTIPLE SELECT GATES OF DIFFERENT RANGES OF THRESHOLD VOLTAGES CONNECTED IN SERIES WITH MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2020
|
Application #:
|
15484744
|
Filing Dt:
|
04/11/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2018
| | | | |
|
Title:
|
TRANSACTION IDENTIFICATION
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15484793
|
Filing Dt:
|
04/11/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2018
| | | | |
|
Title:
|
MEMORY PROTOCOL WITH PROGRAMMABLE BUFFER AND CACHE SIZE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2019
|
Application #:
|
15485696
|
Filing Dt:
|
04/12/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/17/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR VOLTAGE LEVEL CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2019
|
Application #:
|
15485877
|
Filing Dt:
|
04/12/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2018
| | | | |
|
Title:
|
SCALABLE LOW-LATENCY STORAGE INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2018
|
Application #:
|
15487743
|
Filing Dt:
|
04/14/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
METHODS OF FORMING PHASE CHANGE MEMORY APPARATUSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2018
|
Application #:
|
15488328
|
Filing Dt:
|
04/14/2017
|
|
Title:
|
APPARATUSES AND METHODS FOR CONTROLLING WORDLINES AND SENSE AMPLIFIERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2018
|
Application #:
|
15488828
|
Filing Dt:
|
04/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
MEMORIES HAVING A SHARED RESISTANCE VARIABLE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2018
|
Application #:
|
15489276
|
Filing Dt:
|
04/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
ERASABLE BLOCK SEGMENTATION FOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2018
|
Application #:
|
15489311
|
Filing Dt:
|
04/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2018
| | | | |
|
Title:
|
CONSTRUCTION OF INTEGRATED CIRCUITRY AND A METHOD OF FORMING AN ELEVATIONALLY-EXTENDING CONDUCTOR LATERALLY BETWEEN A PAIR OF STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2018
|
Application #:
|
15489342
|
Filing Dt:
|
04/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2018
| | | | |
|
Title:
|
ELEMENT VALUE COMPARISON IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2018
|
Application #:
|
15489434
|
Filing Dt:
|
04/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2018
|
Application #:
|
15489442
|
Filing Dt:
|
04/17/2017
|
|
Title:
|
SIGNED ELEMENT COMPARE IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15490316
|
Filing Dt:
|
04/18/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2018
| | | | |
|
Title:
|
DATA STORAGE WITH DATA RANDOMIZER IN MULTIPLE OPERATING MODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2018
|
Application #:
|
15490327
|
Filing Dt:
|
04/18/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
METHODS AND APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2018
|
Application #:
|
15490536
|
Filing Dt:
|
04/18/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
SYSTEM AND METHOD OF COMMAND BASED AND CURRENT LIMIT CONTROLLED MEMORY DEVICE POWER UP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2018
|
Application #:
|
15490660
|
Filing Dt:
|
04/18/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR FORMING DIE STACKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2018
|
Application #:
|
15490690
|
Filing Dt:
|
04/18/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
DEVICE HAVING MULTIPLE CHANNELS WITH CALIBRATION CIRCUIT SHARED BY MULTIPLE CHANNELS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2018
|
Application #:
|
15490859
|
Filing Dt:
|
04/18/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
SOLID-STATE RADIATION TRANSDUCER DEVICES HAVING FLIP-CHIP MOUNTED SOLID-STATE RADIATION TRANSDUCERS AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2019
|
Application #:
|
15491705
|
Filing Dt:
|
04/19/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
PROGRESSIVE EFFORT DECODER ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2018
|
Application #:
|
15492686
|
Filing Dt:
|
04/20/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A ROLL CALL CIRCUIT FOR OUTPUTTING ADDRESSES OF DEFECTIVE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2020
|
Application #:
|
15493505
|
Filing Dt:
|
04/21/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2018
| | | | |
|
Title:
|
MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS WITH MEMORY MAPS BASED ON MEMORY OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2021
|
Application #:
|
15493551
|
Filing Dt:
|
04/21/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2018
| | | | |
|
Title:
|
APPARATUS AND METHOD TO SWITCH CONFIGURABLE LOGIC UNITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2017
|
Application #:
|
15493772
|
Filing Dt:
|
04/21/2017
|
|
Title:
|
APPARATUSES AND METHODS FOR FLEXIBLE FUSE TRANSMISSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2017
|
Application #:
|
15493816
|
Filing Dt:
|
04/21/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/17/2017
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH SINGLE ENDED MAIN I/O LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2021
|
Application #:
|
15494969
|
Filing Dt:
|
04/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2018
| | | | |
|
Title:
|
Elevationally-Extending String Of Memory Cells And Methods Of Forming An Elevationally-Extending String Of Memory Cells
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2019
|
Application #:
|
15495401
|
Filing Dt:
|
04/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2018
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR PROVIDING WORD LINE VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2019
|
Application #:
|
15503786
|
Filing Dt:
|
02/14/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
ERASING MEMORY CELLS
|
|
