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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	007696/0914			Pages:	4
		Recorded:	10/27/1995
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14

Patent #:	5226126	Issue Dt:	07/06/1993	Application #:	07483223	Filing Dt:	02/21/1990
Title:	PROSESSOR HAVING PLURALITY OF FUNCTIONAL UNITS FOR ORDERLY RETIRING OU TSTANDING OPERATIONS BASED UPON ITS ASSOCIATED TAGS

Patent #:	5230068	Issue Dt:	07/20/1993	Application #:	07485304	Filing Dt:	02/26/1990
Title:	CACHE MEMORY SYSTEM FOR DYNAMICALLY ALTERING SINGLE CACHE MEMORY LINE AS EITHER BRANCH TARGET ENTRY OR PRE-FETCH INSTRUTCHION QUEUE BASED UPON INSTRUCTION SEQUENCE

Patent #:	5093778	Issue Dt:	03/03/1992	Application #:	07485307	Filing Dt:	02/26/1990
Title:	INTEGRATED SINGLE STRUCTURE BRANCH PREDICTION CACHE

Patent #:	5226130	Issue Dt:	07/06/1993	Application #:	07485312	Filing Dt:	02/26/1990
Title:	METHOD AND APPARATUS FOR STORE-INTO-INSTRUCTION-STREAM DETECTION AND MAINTAINING BRANCH PREDICTION CACHE CONSISTENCY

Patent #:	5125093	Issue Dt:	06/23/1992	Application #:	07567399	Filing Dt:	08/14/1990
Title:	INTERRUPT CONTROL FOR MULTIPROCESSOR COMPUTER SYSTEM

Patent #:	5369748	Issue Dt:	11/29/1994	Application #:	07748768	Filing Dt:	08/23/1991
Title:	BUS ARBITRATION IN A DUAL-BUS ARCHITECTURE WHERE ONE BUS HAS RELATIVELY HIGH LATENCY

Patent #:	5163140	Issue Dt:	11/10/1992	Application #:	07844995	Filing Dt:	03/02/1992
Title:	TWO-LEVEL BRANCH PREDICTION CACHE

Patent #:	5327547	Issue Dt:	07/05/1994	Application #:	07954441	Filing Dt:	09/30/1992
Title:	TWO-LEVEL BRANCH PREDICTION CACHE

Patent #:	5388227	Issue Dt:	02/07/1995	Application #:	07958438	Filing Dt:	10/07/1992
Title:	TRANSPARENT DATA BUS SIZING

Patent #:	5442757	Issue Dt:	08/15/1995	Application #:	08025439	Filing Dt:	03/03/1993
Title:	COMPUTER PROCESSOR WITH DISTRIBUTED PIPELINE CONTROL THAT ALLOWS FUNCTIONAL UNITS TO COMPLETE OPERATIONS OUT OF ORDER WHILE MAINTAIN- ING PRECISE INTERRUPTS

Patent #:	5454117	Issue Dt:	09/26/1995	Application #:	08112572	Filing Dt:	08/25/1993
Title:	CONFIGURABLE BRANCH PREDICTION FOR A PROCESSOR PERFORMING SPECULATIVE EXECUTION

Patent #:	5418736	Issue Dt:	05/23/1995	Application #:	08212514	Filing Dt:	03/11/1994
Title:	OPTIMIZED BINARY ADDERS AND COMPARATORS FOR INPUTS HAVING DIFFERENT WIDTHS

Patent #:	5394351	Issue Dt:	02/28/1995	Application #:	08212516	Filing Dt:	03/11/1994
Title:	OPTIMIZED BINARY ADDER AND COMPARATOR HAVING AN IMPLICIT CONSTANT FOR AN INPUT

Patent #:	5414820	Issue Dt:	05/09/1995	Application #:	08215232	Filing Dt:	03/21/1994
Title:	CROSSING TRANSFERS FOR MAXIMIZING THE EFFECTIVE BANDWIDTH IN A DUAL-BUS ARCHITECTURE

Assignor

Exec Dt:

10/20/1995

Assignee

ONE AMD PLACE

SUNNYVALE, CALIFORNIA 94088

Correspondence name and address
	ROBERT O. GUILLOT
	BRONSON, BRONSON & MCKINNON
	10 ALMADEN BLVD., #600
	SAN JOSE, CA 95113

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