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Patent #:
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Issue Dt:
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12/04/2012
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Application #:
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12296919
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Filing Dt:
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12/19/2008
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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PLURAL MATRICES OF EXECUTION UNITS FOR PROCESSING MATRICES OF ROW DEPENDENT INSTRUCTIONS IN SINGLE CLOCK CYCLE IN SUPER OR SEPARATE MODE
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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12514303
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Filing Dt:
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01/05/2010
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Publication #:
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Pub Dt:
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06/24/2010
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Title:
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PARALLEL PROCESSING OF A SEQUENTIAL PROGRAM USING HARDWARE GENERATED THREADS AND THEIR INSTRUCTION GROUPS EXECUTING ON PLURAL EXECUTION UNITS AND ACCESSING REGISTER FILE SEGMENTS USING DEPENDENCY INHERITANCE VECTORS ACROSS MULTIPLE ENGINES
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Patent #:
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Issue Dt:
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07/18/2017
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Application #:
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13359767
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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08/02/2012
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Title:
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GUEST INSTRUCTION TO NATIVE INSTRUCTION RANGE BASED MAPPING USING A CONVERSION LOOK ASIDE BUFFER OF A PROCESSOR
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Patent #:
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Issue Dt:
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01/10/2017
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Application #:
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13359817
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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08/02/2012
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Title:
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GUEST INSTRUCTION BLOCK WITH NEAR BRANCHING AND FAR BRANCHING SEQUENCE CONSTRUCTION TO NATIVE INSTRUCTION BLOCK
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Patent #:
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Issue Dt:
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05/02/2017
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Application #:
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13359832
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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08/02/2012
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Title:
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GUEST TO NATIVE BLOCK ADDRESS MAPPINGS AND MANAGEMENT OF NATIVE CODE STORAGE
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Patent #:
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Issue Dt:
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07/04/2017
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Application #:
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13359939
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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08/02/2012
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Title:
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VARIABLE CACHING STRUCTURE FOR MANAGING PHYSICAL STORAGE
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Patent #:
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Issue Dt:
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12/08/2015
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Application #:
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13359961
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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01/24/2013
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Title:
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MULTILEVEL CONVERSION TABLE CACHE FOR TRANSLATING GUEST INSTRUCTIONS TO NATIVE INSTRUCTIONS
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Patent #:
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Issue Dt:
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08/15/2017
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Application #:
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13360024
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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01/24/2013
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Title:
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Mapping of guest instruction block assembled according to branch prediction to translated native conversion block
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13414456
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Filing Dt:
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03/07/2012
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Publication #:
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Pub Dt:
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09/12/2013
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Title:
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SYSTEMS AND METHODS FOR ACCESSING A UNIFIED TRANSLATION LOOKASIDE BUFFER
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Patent #:
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Issue Dt:
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12/12/2017
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Application #:
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13428438
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Filing Dt:
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03/23/2012
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Publication #:
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Pub Dt:
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09/27/2012
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Title:
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REGISTER FILE SEGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES
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Patent #:
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Issue Dt:
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09/19/2017
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Application #:
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13428440
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Filing Dt:
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03/23/2012
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Publication #:
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Pub Dt:
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09/27/2012
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Title:
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EXECUTING INSTRUCTION SEQUENCE CODE BLOCKS BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES
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Patent #:
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Issue Dt:
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03/01/2016
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Application #:
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13428452
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Filing Dt:
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03/23/2012
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Publication #:
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Pub Dt:
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09/27/2012
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Title:
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MEMORY FRAGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES
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Patent #:
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Issue Dt:
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04/10/2018
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Application #:
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13475708
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Filing Dt:
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05/18/2012
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Publication #:
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Pub Dt:
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11/22/2012
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Title:
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DECENTRALIZED ALLOCATION OF RESOURCES AND INTERCONNECT STRUCTURES TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES
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Patent #:
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Issue Dt:
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09/13/2016
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Application #:
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13475739
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Filing Dt:
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05/18/2012
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Publication #:
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Pub Dt:
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11/22/2012
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Title:
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GLOBAL AND LOCAL INTERCONNECT STRUCTURE COMPRISING ROUTING MATRIX TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES
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Patent #:
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Issue Dt:
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08/22/2017
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Application #:
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13561441
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Filing Dt:
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07/30/2012
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Publication #:
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Pub Dt:
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01/30/2014
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Title:
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SYSTEMS AND METHODS FOR MAINTAINING THE COHERENCY OF A STORE COALESCING CACHE AND A LOAD CACHE
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Patent #:
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Issue Dt:
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07/18/2017
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Application #:
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13561491
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Filing Dt:
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07/30/2012
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Publication #:
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Pub Dt:
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01/30/2014
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Title:
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SYSTEMS AND METHODS FOR FLUSHING A CACHE WITH MODIFIED DATA
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Patent #:
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Issue Dt:
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08/30/2016
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Application #:
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13561528
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Filing Dt:
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07/30/2012
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Publication #:
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Pub Dt:
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01/30/2014
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Title:
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SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD ACCESSES OF A CACHE IN A SINGLE CYCLE
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Patent #:
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Issue Dt:
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01/05/2016
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Application #:
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13561570
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Filing Dt:
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07/30/2012
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Publication #:
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Pub Dt:
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01/30/2014
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Title:
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SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD AND STORE ACCESSES OF A CACHE
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Patent #:
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Issue Dt:
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05/24/2016
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Application #:
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13649469
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Filing Dt:
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10/11/2012
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Publication #:
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Pub Dt:
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04/17/2014
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Title:
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SYSTEMS AND METHODS FOR IMPLEMENTING WEAK STREAM SOFTWARE DATA AND INSTRUCTION PREFETCHING USING A HARDWARE DATA PREFETCHER
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Patent #:
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Issue Dt:
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08/23/2016
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Application #:
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13649505
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Filing Dt:
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10/11/2012
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Publication #:
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Pub Dt:
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04/17/2014
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Title:
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SYSTEMS AND METHODS FOR LOAD CANCELING IN A PROCESSOR THAT IS CONNECTED TO AN EXTERNAL INTERCONNECT FABRIC
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Patent #:
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Issue Dt:
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06/13/2017
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Application #:
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13649532
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Filing Dt:
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10/11/2012
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Publication #:
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Pub Dt:
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04/17/2014
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Title:
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SYSTEMS AND METHODS FOR NON-BLOCKING IMPLEMENTATION OF CACHE FLUSH INSTRUCTIONS
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13691609
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Filing Dt:
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11/30/2012
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Publication #:
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Pub Dt:
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04/11/2013
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Title:
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Processor executing super instruction matrix with register file configurable for single or multiple threads operations
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Patent #:
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Issue Dt:
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03/12/2019
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Application #:
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13824013
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Filing Dt:
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07/11/2016
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Publication #:
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Pub Dt:
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09/14/2017
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Title:
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SINGLE CYCLE MULTI-BRANCH PREDICTION INCLUDING SHADOW CACHE FOR EARLY FAR BRANCH PREDICTION
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Patent #:
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Issue Dt:
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06/13/2017
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Application #:
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13879365
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Filing Dt:
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08/12/2013
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Publication #:
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Pub Dt:
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11/21/2013
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Title:
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INSTRUCTION SEQUENCE BUFFER TO ENHANCE BRANCH PREDICTION EFFICIENCY
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Patent #:
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Issue Dt:
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08/15/2017
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Application #:
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13879374
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Filing Dt:
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11/27/2013
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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INSTRUCTION SEQUENCE BUFFER TO STORE BRANCHES HAVING RELIABLY PREDICTABLE INSTRUCTION SEQUENCES
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Patent #:
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Issue Dt:
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04/25/2017
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Application #:
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13970277
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Filing Dt:
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08/19/2013
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Publication #:
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Pub Dt:
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02/19/2015
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Title:
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SYSTEMS AND METHODS FOR ACQUIRING DATA FOR LOADS AT DIFFERENT ACCESS TIMES FROM HIERARCHICAL SOURCES USING A LOAD QUEUE AS A TEMPORARY STORAGE BUFFER AND COMPLETING THE LOAD EARLY
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Patent #:
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Issue Dt:
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04/11/2017
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Application #:
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13970311
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Filing Dt:
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08/19/2013
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Publication #:
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Pub Dt:
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02/19/2015
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Title:
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SYSTEMS AND METHODS FOR READ REQUEST BYPASSING A LAST LEVEL CACHE THAT INTERFACES WITH AN EXTERNAL FABRIC
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Patent #:
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Issue Dt:
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05/30/2017
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Application #:
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13970344
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Filing Dt:
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08/19/2013
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Publication #:
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Pub Dt:
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02/19/2015
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Title:
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SYSTEMS AND METHODS FOR INVASIVE DEBUG OF A PROCESSOR WITHOUT PROCESSOR EXECUTION OF INSTRUCTIONS
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Patent #:
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Issue Dt:
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06/07/2016
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Application #:
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14015086
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Filing Dt:
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08/30/2013
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Publication #:
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Pub Dt:
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03/05/2015
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Title:
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SYSTEMS AND METHODS FOR FASTER READ AFTER WRITE FORWARDING USING A VIRTUAL ADDRESS
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Patent #:
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Issue Dt:
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09/06/2016
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Application #:
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14052571
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Filing Dt:
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10/11/2013
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
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Title:
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Method and Apparatus for Sorting Elements in Hardware Structures
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Patent #:
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Issue Dt:
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02/05/2019
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Application #:
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14063173
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Filing Dt:
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10/25/2013
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
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Title:
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MICROPROCESSOR FOR GATING A LOAD OPERATION BASED ON ENTRIES OF A PREDICTION TABLE
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Patent #:
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Issue Dt:
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12/11/2018
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Application #:
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14063409
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Filing Dt:
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10/25/2013
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
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Title:
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APPARATUS FOR GATING A LOAD OPERATION BASED ON ENTRIES OF A PREDICTION TABLE
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Patent #:
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Issue Dt:
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02/28/2017
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Application #:
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14101615
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Filing Dt:
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12/10/2013
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
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Title:
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METHOD AND APPARATUS TO AVOID DEADLOCK DURING INSTRUCTION SCHEDULING USING DYNAMIC PORT REMAPPING
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Patent #:
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Issue Dt:
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04/25/2017
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Application #:
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14107116
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Filing Dt:
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12/16/2013
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Publication #:
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Pub Dt:
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12/18/2014
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Title:
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METHOD AND APPARATUS FOR EFFICIENT SCHEDULING FOR ASYMMETRICAL EXECUTION UNITS
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Patent #:
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Issue Dt:
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03/13/2018
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Application #:
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14173602
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Filing Dt:
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02/05/2014
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
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Title:
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METHOD AND APPARATUS FOR SUPPORTING A PLURALITY OF LOAD ACCESSES OF A CACHE IN A SINGLE CYCLE TO MAINTAIN THROUGHPUT
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Patent #:
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Issue Dt:
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03/28/2017
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Application #:
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14182618
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Filing Dt:
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02/18/2014
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Publication #:
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Pub Dt:
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10/23/2014
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Title:
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METHOD AND APPARATUS FOR PREVENTING NON-TEMPORAL ENTRIES FROM POLLUTING SMALL STRUCTURES USING A TRANSIENT BUFFER
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Patent #:
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Issue Dt:
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11/22/2016
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Application #:
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14194589
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Filing Dt:
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02/28/2014
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Publication #:
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Pub Dt:
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06/26/2014
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Title:
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CACHE STORING DATA FETCHED BY ADDRESS CALCULATING LOAD INSTRUCTION WITH LABEL USED AS ASSOCIATED NAME FOR CONSUMING INSTRUCTION TO REFER
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Patent #:
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Issue Dt:
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11/05/2019
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Application #:
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14209736
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Filing Dt:
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03/13/2014
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Publication #:
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Pub Dt:
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09/18/2014
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Title:
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METHOD AND APPARATUS FOR NEAREST POTENTIAL STORE TAGGING
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Patent #:
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Issue Dt:
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12/24/2019
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Application #:
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14211476
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
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Title:
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Method and Apparatus to Allow Early Dependency Resolution and Data Forwarding in a Microprocessor
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Patent #:
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Issue Dt:
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03/12/2019
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Application #:
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14211655
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
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Title:
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Method and Apparatus for Guest Return Address Stack Emulation Supporting Speculation
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14211878
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
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Title:
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Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14212203
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
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02/12/2015
| | | | |
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Title:
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METHOD FOR USING REGISTER TEMPLATES TO TRACK INTERDEPENDENCIES AMONG BLOCKS OF INSTRUCTIONS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14212533
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
|
02/12/2015
| | | | |
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Title:
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METHOD FOR EXECUTING BLOCKS OF INSTRUCTIONS USING A MICROPROCESSOR ARCHITECTURE HAVING A REGISTER VIEW, SOURCE VIEW, INSTRUCTION VIEW, AND A PLURALITY OF REGISTER TEMPLATES
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Patent #:
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Issue Dt:
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02/14/2017
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Application #:
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14213115
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
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Title:
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METHOD FOR POPULATING A SOURCE VIEW DATA STRUCTURE BY USING REGISTER TEMPLATE SNAPSHOTS
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Patent #:
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Issue Dt:
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04/30/2019
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Application #:
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14213135
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Filing Dt:
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03/14/2014
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|
Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
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Title:
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METHOD FOR DEPENDENCY BROADCASTING THROUGH A SOURCE ORGANIZED SOURCE VIEW DATA STRUCTURE
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Patent #:
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Issue Dt:
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11/07/2017
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Application #:
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14213218
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
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10/23/2014
| | | | |
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Title:
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METHOD FOR PERFORMING DUAL DISPATCH OF BLOCKS AND HALF BLOCKS
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Patent #:
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Issue Dt:
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01/02/2018
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Application #:
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14213692
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
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Title:
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METHOD FOR IMPLEMENTING A REDUCED SIZE REGISTER VIEW DATA STRUCTURE IN A MICROPROCESSOR
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Patent #:
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Issue Dt:
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11/21/2017
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Application #:
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14213730
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
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Title:
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METHOD FOR EMULATING A GUEST CENTRALIZED FLAG ARCHITECTURE BY USING A NATIVE DISTRIBUTED FLAG ARCHITECTURE
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Patent #:
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Issue Dt:
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02/21/2017
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Application #:
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14213854
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
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Title:
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METHOD FOR POPULATING REGISTER VIEW DATA STRUCTURE BY USING REGISTER TEMPLATE SNAPSHOTS
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Patent #:
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Issue Dt:
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08/22/2017
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Application #:
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14213909
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Filing Dt:
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03/14/2014
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
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Title:
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METHOD FOR IMPLEMENTING A LINE SPEED INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
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02/06/2018
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Application #:
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14214045
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Filing Dt:
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03/14/2014
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Publication #:
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09/18/2014
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09/05/2017
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14214049
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03/14/2014
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10/30/2014
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METHOD FOR A STAGE OPTIMIZED HIGH SPEED ADDER
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02/13/2018
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14214176
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03/14/2014
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09/18/2014
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Title:
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METHOD FOR IMPLEMENTING A REDUCED SIZE REGISTER VIEW DATA STRUCTURE IN A MICROPROCESSOR
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11/07/2017
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14214280
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03/14/2014
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09/18/2014
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02/27/2018
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14215633
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03/17/2014
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09/18/2014
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Title:
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METHODS, SYSTEMS AND APPARATUS FOR PREDICTING THE WAY OF A SET ASSOCIATIVE CACHE
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11/27/2018
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14216493
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03/17/2014
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09/18/2014
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Title:
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METHODS, SYSTEMS AND APPARATUS FOR SUPPORTING WIDE AND EFFICIENT FRONT-END OPERATION WITH GUEST-ARCHITECTURE EMULATION
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11/14/2017
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14216683
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03/17/2014
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09/18/2014
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Title:
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METHOD FOR A DELAYED BRANCH IMPLEMENTATION BY USING A FRONT END TRACK TABLE
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04/18/2017
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14216855
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03/17/2014
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01/22/2015
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Title:
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MULTIPORT MEMORY CELL HAVING IMPROVED DENSITY AREA
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04/03/2018
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14216859
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03/17/2014
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09/18/2014
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Title:
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METHOD FOR DEPENDENCY BROADCASTING THROUGH A BLOCK ORGANIZED SOURCE VIEW DATA STRUCTURE
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02/13/2018
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14281663
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05/19/2014
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10/09/2014
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METHOD AND APPARATUS TO INCREASE THE SPEED OF THE LOAD ACCESS AND DATA RETURN SPEED PATH USING EARLY LOWER ADDRESS BITS
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NONE
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14360280
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07/29/2014
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11/20/2014
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Title:
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MICROPROCESSOR ACCELERATED CODE OPTIMIZER AND DEPENDENCY REORDERING METHOD
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NONE
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14360282
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09/15/2014
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02/05/2015
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Title:
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MICROPROCESSOR ACCELERATED CODE OPTIMIZER
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01/29/2019
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14360284
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10/06/2014
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07/02/2015
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Title:
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ACCELERATED CODE OPTIMIZER FOR A MULTIENGINE MICROPROCESSOR
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07/23/2019
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14376825
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05/19/2015
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09/03/2015
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Title:
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FAST UNALIGNED MEMORY ACCESS
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03/27/2018
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14385968
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05/07/2015
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10/08/2015
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Title:
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CACHE REPLACEMENT POLICY
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09/11/2018
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14515333
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10/15/2014
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04/21/2016
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METHODS AND SYSTEMS FOR TRACKING ADDRESSES STORED IN NON-HOME CACHE LOCATIONS
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09/11/2018
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14515345
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10/15/2014
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04/21/2016
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Title:
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SYSTEMS AND METHODS FOR INVALIDATING DIRECTORY OF NON-HOME LOCATIONS WAYS
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06/13/2017
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14515379
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10/15/2014
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SYSTEMS AND METHODS FOR MANAGING INTER-CPU INTERRUPTS BETWEEN MULTIPLE CPUs
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02/27/2018
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14559740
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12/03/2014
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05/14/2015
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Title:
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VIRTUAL LOAD STORE QUEUE HAVING A DYNAMIC DISPATCH WINDOW WITH A DISTRIBUTED STRUCTURE
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NONE
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14560974
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12/04/2014
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04/02/2015
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Title:
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METHOD AND SYSTEM FOR FILTERING THE STORES TO PREVENT ALL STORES FROM HAVING TO SNOOP CHECK AGAINST ALL WORDS OF A CACHE
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NONE
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14563583
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12/08/2014
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04/02/2015
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Title:
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LOCK-BASED AND SYNCH-BASED METHOD FOR OUT OF ORDER LOADS IN A MEMORY CONSISTENCY MODEL USING SHARED MEMORY RESOURCES
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03/27/2018
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14567699
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12/11/2014
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04/02/2015
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Title:
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METHOD AND SYSTEM FOR IMPLEMENTING RECOVERY FROM SPECULATIVE FORWARDING MISS-PREDICTIONS/ERRORS RESULTING FROM LOAD STORE REORDERING AND OPTIMIZATION
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06/05/2018
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14567731
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12/11/2014
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04/02/2015
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Title:
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INSTRUCTION DEFINITION TO IMPLEMENT LOAD STORE REORDERING AND OPTIMIZATION
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05/08/2018
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14567797
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12/11/2014
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04/02/2015
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Title:
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VIRTUAL LOAD STORE QUEUE HAVING A DYNAMIC DISPATCH WINDOW WITH A UNIFIED STRUCTURE
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NONE
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14569537
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12/12/2014
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Pub Dt:
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04/09/2015
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Title:
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SEMAPHORE METHOD AND SYSTEM WITH OUT OF ORDER LOADS IN A MEMORY CONSISTENCY MODEL THAT CONSTITUTES LOADS READING FROM MEMORY IN ORDER
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08/14/2018
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14569543
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12/12/2014
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04/09/2015
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Title:
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DISAMBIGUATION-FREE OUT OF ORDER LOAD STORE QUEUE
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07/10/2018
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14569551
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12/12/2014
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04/09/2015
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Title:
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REORDERED SPECULATIVE INSTRUCTION SEQUENCES WITH A DISAMBIGUATION-FREE OUT OF ORDER LOAD STORE QUEUE
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NONE
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14569554
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12/12/2014
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07/23/2015
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Title:
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LOAD STORE BUFFER AGNOSTIC TO THREADS IMPLEMENTING FORWARDING FROM DIFFERENT THREADS BASED ON STORE SENIORITY
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09/27/2016
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14590902
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01/06/2015
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10/22/2015
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Title:
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SYSTEMS AND METHODS FOR ACCESSING A UNIFIED TRANSLATION LOOKASIDE BUFFER
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04/17/2018
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14710372
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05/12/2015
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Pub Dt:
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11/12/2015
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METHOD AND APPARATUS FOR PROVIDING HARDWARE SUPPORT FOR SELF-MODIFYING CODE
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02/06/2018
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14733827
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06/08/2015
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09/24/2015
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Title:
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Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations
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03/22/2022
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14806169
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07/22/2015
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01/28/2016
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Title:
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USING A PLURALITY OF CONVERSION TABLES TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE
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NONE
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14807141
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07/23/2015
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01/28/2016
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Title:
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AN ALLOCATION AND ISSUE STAGE FOR REORDERING A MICROINSTRUCTION SEQUENCE INTO AN OPTIMIZED MICROINSTRUCTION SEQUENCE TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE
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11/21/2017
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14807271
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07/23/2015
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01/28/2016
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Title:
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SYSTEM FOR AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE
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08/15/2017
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14807308
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07/23/2015
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01/28/2016
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Title:
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SYSTEM CONVERTER THAT IMPLEMENTS A REORDERING PROCESS THROUGH JIT (JUST IN TIME) OPTIMIZATION THAT ENSURES LOADS DO NOT DISPATCH AHEAD OF OTHER LOADS THAT ARE TO THE SAME ADDRESS
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NONE
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14807313
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07/23/2015
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Pub Dt:
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01/28/2016
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Title:
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USING A CONVERSION LOOK ASIDE BUFFER TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE
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NONE
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14807343
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07/23/2015
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01/28/2016
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Title:
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SYSTEM CONVERTER THAT EXECUTES A JUST IN TIME OPTIMIZER FOR EXECUTING CODE FROM A GUEST IMAGE
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07/16/2019
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14807353
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07/23/2015
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Pub Dt:
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01/28/2016
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Title:
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SYSTEM CONVERTER THAT IMPLEMENTS A RUN AHEAD RUN TIME GUEST INSTRUCTION CONVERSION/DECODING PROCESS AND A PREFETCHING PROCESS WHERE GUEST CODE IS PRE-FETCHED FROM THE TARGET OF GUEST BRANCHES IN AN INSTRUCTION SEQUENCE
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09/19/2017
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14819255
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08/05/2015
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Pub Dt:
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11/26/2015
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Title:
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SYSTEMS AND METHODS FOR FASTER READ AFTER WRITE FORWARDING USING A VIRTUAL ADDRESS
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02/18/2020
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14825502
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08/13/2015
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Pub Dt:
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08/04/2016
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Title:
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METHODS AND SYSTEMS FOR MANAGING SYNONYMS IN VIRTUALLY INDEXED PHYSICALLY TAGGED CACHES
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08/01/2017
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14922035
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10/23/2015
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02/11/2016
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Title:
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SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD AND STORE ACCESSES OF A CACHE
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08/01/2017
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14922042
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10/23/2015
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02/11/2016
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Title:
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SYSTEMS AND METHODS FOR MAINTAINING THE COHERENCY OF A STORE COALESCING CACHE AND A LOAD CACHE
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NONE
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14922053
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10/23/2015
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Pub Dt:
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02/11/2016
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Title:
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SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD ACCESSES OF A CACHE IN A SINGLE CYCLE
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01/22/2019
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14961464
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12/07/2015
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06/08/2017
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Title:
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MULTILEVEL CONVERSION TABLE CACHE FOR TRANSLATING GUEST INSTRUCTIONS TO NATIVE INSTRUCTIONS
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12/12/2017
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15003486
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01/21/2016
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Pub Dt:
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05/19/2016
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Title:
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SYSTEMS AND METHODS FOR NON-BLOCKING IMPLEMENTATION OF CACHE FLUSH INSTRUCTIONS
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09/05/2017
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15009684
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01/28/2016
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08/04/2016
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Title:
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VARIABLE CACHING STRUCTURE FOR MANAGING PHYSICAL STORAGE
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03/20/2018
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15019920
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02/09/2016
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Pub Dt:
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06/02/2016
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Title:
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MEMORY FRAGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES
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Patent #:
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NONE
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Application #:
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15042005
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02/11/2016
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Pub Dt:
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01/26/2017
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Title:
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HARDWARE ACCELERATION COMPONENTS FOR TRANSLATING GUEST INSTRUCTIONS TO NATIVE INSTRUCTIONS
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06/05/2018
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Application #:
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15082359
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03/28/2016
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Publication #:
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Pub Dt:
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07/21/2016
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Title:
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EXECUTING INSTRUCTION SEQUENCE CODE BLOCKS BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES
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04/03/2018
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Application #:
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15082867
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03/28/2016
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Pub Dt:
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07/21/2016
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Title:
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REGISTER FILE SEGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES
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