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Total properties:
30
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Patent #:
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|
Issue Dt:
|
01/26/1993
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Application #:
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07773827
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Filing Dt:
|
10/09/1991
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Title:
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ARRAY LAYOUT STRUCTURE FOR IMPLEMENTING LARGE HIGH-DENSITY ADDRESS DECODERS FOR GATE ARRAY MEMORIES
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|
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Patent #:
|
|
Issue Dt:
|
10/31/1995
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Application #:
|
08082867
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Filing Dt:
|
06/29/1993
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Title:
|
METHOD AND APPARATUS FOR DETERMINING ERROR LOCATION
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|
|
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Patent #:
|
|
Issue Dt:
|
08/08/1995
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Application #:
|
08082869
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Filing Dt:
|
06/29/1993
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Title:
|
METHOD OF AND SYSTEM FOR LAYING OUT BUS CELLS ON AN INTEGRATED CIRCUIT CHIP
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|
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Patent #:
|
|
Issue Dt:
|
01/17/1995
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Application #:
|
08082870
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Filing Dt:
|
06/29/1993
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Title:
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PARALLEL ENCODING APPARATUS AND METHOD IMPLEMENTING CYCLIC REDUNDANCY CHECK AND REED-SOLOMON CODES
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|
|
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Patent #:
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Issue Dt:
|
08/29/1995
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Application #:
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08150897
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Filing Dt:
|
11/12/1993
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Title:
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APPARATUS FOR CORRECTING ERRORS IN OPTICAL DISKS
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|
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Patent #:
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|
Issue Dt:
|
06/24/1997
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Application #:
|
08192909
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Filing Dt:
|
02/07/1994
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Title:
|
FINITE FIELD POLYNOMIAL PROCESSING MODULE FOR ERROR CONTROL CODING
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|
|
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Patent #:
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|
Issue Dt:
|
08/29/1995
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Application #:
|
08225690
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Filing Dt:
|
04/11/1994
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|
Title:
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VERTICAL DETAIL ENHANCEMENT WITH STEPPED RETURN CORING
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|
|
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Patent #:
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|
Issue Dt:
|
01/23/1996
|
Application #:
|
08316462
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Filing Dt:
|
09/30/1994
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|
Title:
|
CMOS LEVEL SHIFTER WITH FEEDFORWARD CONTROL TO PREVENT LATCHING IN A WRONG LOGIC STATE
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|
|
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Patent #:
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|
Issue Dt:
|
04/30/1996
|
Application #:
|
08493016
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Filing Dt:
|
06/21/1995
|
|
Title:
|
HIERARCHICAL FLOORPLANNER FOR GATE ARRAY DESIGN LAYOUT
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/10/1998
|
Application #:
|
08561756
|
Filing Dt:
|
11/22/1995
|
|
Title:
|
HIGH BIT RATE START CODE SEARCHING AND DETECTING CIRCUIT AND METHOD
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|
|
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Patent #:
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|
Issue Dt:
|
06/16/1998
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Application #:
|
08567592
|
Filing Dt:
|
12/05/1995
|
|
Title:
|
LOW POWER HIGH SPEED MPEG VIDEO VARIABLE LENGTH DECODER
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|
|
|
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Patent #:
|
|
Issue Dt:
|
12/01/1998
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Application #:
|
08612512
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Filing Dt:
|
03/07/1996
|
|
Title:
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MPEG ENCODING AND DECODING SYSTEM FOR MULTIMEDIA APPLICATIONS
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|
|
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Patent #:
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|
Issue Dt:
|
10/21/1997
|
Application #:
|
08648795
|
Filing Dt:
|
05/16/1996
|
|
Title:
|
SHARED DRAM I/O DATABUS FOR HIGH SPEED OPERATION
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/21/1998
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Application #:
|
08655132
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Filing Dt:
|
05/30/1996
|
|
Title:
|
AUTOMATIC SOFTWARE LICENSE MANAGER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/1998
|
Application #:
|
08659599
|
Filing Dt:
|
06/06/1996
|
|
Title:
|
BUFFER WITH DRIVE CHARACTERISTICS CONTROLLABLE BY SOFTWARE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/11/1998
|
Application #:
|
08760007
|
Filing Dt:
|
12/03/1996
|
|
Title:
|
MICRO ROM TESTING SYSTEM USING MICRO ROM TIMING CIRCUITS FOR TESTING OPERATIONS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/25/1998
|
Application #:
|
08767135
|
Filing Dt:
|
12/19/1996
|
|
Title:
|
HIGH-SPEED MAIN AMPLIFIER WITH REDUCED ACCESS AND OUTPUT DISABLE TIME PERIODS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/21/1998
|
Application #:
|
08781388
|
Filing Dt:
|
01/13/1997
|
|
Title:
|
LATCHED DRAM WRITE BUS FOR QUICKLY CLEARING DRAM ARRAY WITH MINIMUM POWER USAGE
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/25/2000
|
Application #:
|
08828780
|
Filing Dt:
|
03/27/1997
|
|
Title:
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DMA CONTROLLER WITH SEMAPHORE COMMUNICATION PROTOCOL
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|
|
|
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Patent #:
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|
Issue Dt:
|
11/17/1998
|
Application #:
|
08845840
|
Filing Dt:
|
04/28/1997
|
|
Title:
|
THREE-TRANSISTOR STATIC STORAGE CELL
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/31/1999
|
Application #:
|
08954628
|
Filing Dt:
|
10/20/1997
|
|
Title:
|
RAM HAVING MULTIPLE PORTS SHARING COMMON MEMORY LOCATIONS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/31/2000
|
Application #:
|
08984076
|
Filing Dt:
|
12/03/1997
|
|
Title:
|
GROUNDED PACKAGED SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/26/2000
|
Application #:
|
09006190
|
Filing Dt:
|
01/13/1998
|
|
Title:
|
MULTI-PORT RAM HAVING FUNCTIONALLY IDENTICAL PORTS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09006191
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Filing Dt:
|
01/13/1998
|
|
Title:
|
MUTI-PORT MEMORY DEVIVE HAVING MASKING REGISTERS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09012460
|
Filing Dt:
|
01/23/1998
|
|
Title:
|
INDEPENDENT CHIP SELECT FOR SRAM AND DRAM IN A MULTI-PORT RAM
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/11/2000
|
Application #:
|
09018343
|
Filing Dt:
|
02/04/1998
|
|
Title:
|
ADDRESSING SYSTEM IN A MULTI-PORT RAM HAVING MAIN AND CACHE MEMORIES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
09024559
|
Filing Dt:
|
02/17/1998
|
|
Title:
|
DUAL CLOCKING SCHEME IN A MULTI-PORT RAM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2002
|
Application #:
|
09587980
|
Filing Dt:
|
06/06/2000
|
|
Title:
|
SYSTEM AND METHOD FOR TERMINAL SHORT DETECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09589118
|
Filing Dt:
|
06/08/2000
|
|
Title:
|
Method and apparatus for amplifier output biasing for improved overall temperature stability
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09589187
|
Filing Dt:
|
06/08/2000
|
|
Title:
|
METHOD AND APPARATUS FOR SWITCHING STAGES OF A MULTISTAGE AMPLIFIER QUICKLY BETWEEN OPERATIONAL MODES
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|
