Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 042431/0916 | |
| Pages: | 8 |
| | Recorded: | 05/18/2017 | | |
| Attorney Dkt #: | SAN-999 (MERGERS) |
| Conveyance: | MERGER (SEE DOCUMENT FOR DETAILS). |
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Total properties:
9
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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10383139
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Filing Dt:
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03/06/2003
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Publication #:
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Pub Dt:
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09/09/2004
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Title:
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METHOD FOR OPTIMIZING HIGH FREQUENCY PERFORMANCE OF VIA STRUCTURES
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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10482832
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Filing Dt:
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12/31/2003
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Publication #:
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Pub Dt:
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09/16/2004
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Title:
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COOLING AIRFLOW DISTRIBUTION DEVICE
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10648407
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Filing Dt:
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08/25/2003
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Publication #:
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Pub Dt:
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03/04/2004
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Title:
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INTERCONNECT FOR ELECTRICALLY CONNECTING A MULTICHIP MODULE TO A CIRCUIT SUBSTRATE AND PROCESSES FOR MAKING AND USING SAME
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Patent #:
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Issue Dt:
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06/19/2007
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Application #:
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10730460
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Filing Dt:
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12/08/2003
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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TEMPERATURE-CONTROLLED FLEXIBLE OPTICAL CIRCUIT FOR USE IN AN ERBIUM-DOPED FIBER AMPLIFIER AND METHOD FOR FABRICATING THE FLEXIBLE OPTICAL CIRCUIT
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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11086691
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Filing Dt:
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03/21/2005
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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TEMPERATURE CONTROL IN AN OPTICAL AMPLIFICATION SYSTEM
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11255523
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Filing Dt:
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10/20/2005
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Publication #:
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Pub Dt:
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04/26/2007
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Title:
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VIA STUB TERMINATION STRUCTURES AND METHODS FOR MAKING SAME
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Patent #:
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Issue Dt:
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02/14/2012
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Application #:
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11720435
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Filing Dt:
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06/05/2008
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Publication #:
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Pub Dt:
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01/08/2009
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Title:
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SYSTEMS AND METHODS FOR BASE STATION ENCLOSURES
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Patent #:
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Issue Dt:
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07/17/2012
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Application #:
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12483223
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Filing Dt:
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06/11/2009
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Publication #:
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Pub Dt:
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11/26/2009
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Title:
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SIMULTANEOUS AND SELECTIVE PARTITIONING OF VIA STRUCTURES USING PLATING RESIST
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Patent #:
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Issue Dt:
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02/18/2014
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Application #:
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13236416
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Filing Dt:
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09/19/2011
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Publication #:
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Pub Dt:
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06/21/2012
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Title:
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MEMORY BUS ARCHITECTURE FOR CONCURRENTLY SUPPORTING VOLATILE AND NON-VOLATILE MEMORY MODULES
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Assignee
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| 2700 NORTH FIRST STREET |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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LOZA & LOZA LLP
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305 NORTH SECOND AVE., #127
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UPLAND, CA 91786-6064
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