Total properties:
88
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09586664
|
Filing Dt:
|
06/01/2000
|
Title:
|
Low power voltage regulator circuit for use in an integrated circuit device
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09602108
|
Filing Dt:
|
06/21/2000
|
Title:
|
Reference cell for high speed sensing in non-volatile memories
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
10174632
|
Filing Dt:
|
06/18/2002
|
Title:
|
ROW DECODER CIRCUIT FOR USE IN PROGRAMMING A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
10190374
|
Filing Dt:
|
07/02/2002
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
Title:
|
METHOD OF PROGRAMMING A MULTI-LEVEL MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
10211437
|
Filing Dt:
|
08/02/2002
|
Title:
|
METHOD OF ESTABLISHING REFERENCE LEVELS FOR SENSING MULTILEVEL MEMORY CELL STATES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
10235265
|
Filing Dt:
|
09/04/2002
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
Title:
|
METHOD OF RECOVERING OVERERASED BITS IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10284597
|
Filing Dt:
|
10/30/2002
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
Title:
|
METHOD FOR IDENTIFICATION OF SPI COMPATIBLE SERIAL MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10326367
|
Filing Dt:
|
12/20/2002
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
Title:
|
CURRENT SENSE AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10666324
|
Filing Dt:
|
09/17/2003
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
DUAL STAGE VOLTAGE REGULATION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10686243
|
Filing Dt:
|
10/14/2003
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
METHOD AND APPARATUS OF A SMART DECODING SCHEME FOR FAST SYNCHRONOUS READ IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10686401
|
Filing Dt:
|
10/14/2003
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
FUNCTIONAL REGISTER DECODING SYSTEM FOR MULTIPLE PLANE OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
10722576
|
Filing Dt:
|
11/28/2003
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
MEMORY SYSTEM AND PROCESS FOR CONTROLLING A MEMORY COMPONENT TO ACHIEVE DIFFERENT KINDS OF MEMORY CHARACTERISTICS ON ONE AND THE SAME MEMORY COMPONENT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
10929899
|
Filing Dt:
|
08/30/2004
|
Title:
|
APPROACH FOR ZERO DUMMY BYTE FLASH MEMORY READ OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11074946
|
Filing Dt:
|
03/09/2005
|
Publication #:
|
|
Pub Dt:
|
09/15/2005
| | | | |
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11076027
|
Filing Dt:
|
03/10/2005
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT INCLUDING AN ELECTROLYTE MATERIAL LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11113332
|
Filing Dt:
|
04/25/2005
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
Title:
|
RESISTIVELY SWITCHING MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11115953
|
Filing Dt:
|
04/27/2005
|
Publication #:
|
|
Pub Dt:
|
11/17/2005
| | | | |
Title:
|
SEMICONDUCTOR MEMORY COMPONENT IN CROSS-POINT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
|
Application #:
|
11131017
|
Filing Dt:
|
05/17/2005
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
Title:
|
REDUNDANT COLUMN READ IN A MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
11133716
|
Filing Dt:
|
05/20/2005
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHOD FOR OPERATING AN INTEGRATED CIRCUIT HAVING A RESISTIVITY CHANGING MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2009
|
Application #:
|
11144174
|
Filing Dt:
|
06/02/2005
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR REDUCING SOFT-WRITING IN A MULTI-LEVEL FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
11153964
|
Filing Dt:
|
06/16/2005
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
METHOD FOR PRODUCING MEMORY HAVING A SOLID ELECTROLYTE MATERIAL REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11190722
|
Filing Dt:
|
07/27/2005
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
CHANNEL DISCHARGING AFTER ERASING FLASH MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11197746
|
Filing Dt:
|
08/05/2005
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
METHOD FOR FABRICATING AN INTEGRATED DEVICE COMPRISING A STRUCTURE WITH A SOLID ELECTROLYTE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11204569
|
Filing Dt:
|
08/16/2005
|
Publication #:
|
|
Pub Dt:
|
02/22/2007
| | | | |
Title:
|
A MEMORY DEVICE INCLUDING ELECTRICAL CIRCUIT CONFIGURED TO PROVIDE REVERSIBLE BIAS ACROSS THE PMC MEMORY CELL TO PERFORM ERASE AND WRITE FUNCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
11209424
|
Filing Dt:
|
08/23/2005
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
MEMORY HAVING CBRAM MEMORY CELLS AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11214692
|
Filing Dt:
|
08/29/2005
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
MEMORY COMPONENT WITH MEMORY CELLS HAVING CHANGEABLE RESISTANCE AND FABRICATION METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11215443
|
Filing Dt:
|
08/30/2005
|
Publication #:
|
|
Pub Dt:
|
03/09/2006
| | | | |
Title:
|
RESISTIVE MEMORY ARRANGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11238117
|
Filing Dt:
|
09/29/2005
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
METHOD FOR MANUFACTURING A CBRAM SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11261212
|
Filing Dt:
|
10/28/2005
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
METHOD FOR IMPROVING THE THERMAL CHARACTERISTICS OF SEMICONDUCTOR MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11276758
|
Filing Dt:
|
03/13/2006
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
READ, WRITE AND ERASE CIRCUIT FOR PROGRAMMABLE MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
11295878
|
Filing Dt:
|
12/07/2005
|
Title:
|
COLUMN/SECTOR REDUNDANCY CAM FAST PROGRAMMING SCHEME USING REGULAR MEMORY CORE ARRAY IN MULTI-PLANE FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
11337940
|
Filing Dt:
|
01/23/2006
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
PMC MEMORY CIRCUIT AND METHOD FOR STORING A DATUM IN A PMC MEMORY CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11341902
|
Filing Dt:
|
01/27/2006
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
INTEGRATED SEMICONDUCTOR MEMORY WITH AN ARRANGEMENT OF NONVOLATILE MEMORY CELLS, AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11344533
|
Filing Dt:
|
02/01/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
METHOD FOR FABRICATING A RESISTIVE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2009
|
Application #:
|
11346571
|
Filing Dt:
|
02/03/2006
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
RESISTIVE MEMORY ELEMENT WITH SHORTENED ERASE TIME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11377633
|
Filing Dt:
|
03/16/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
SOLID ELECTROLYTE MEMORY ELEMENT AND METHOD FOR FABRICATING SUCH A MEMORY ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
11399744
|
Filing Dt:
|
04/07/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
MEMORY CELL, MEMORY DEVICE AND METHOD FOR THE PRODUCTION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11411994
|
Filing Dt:
|
04/26/2006
|
Publication #:
|
|
Pub Dt:
|
11/01/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT INCLUDING RESISTIVITY CHANGING MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
11492305
|
Filing Dt:
|
07/25/2006
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
MEMORY CELLS WITH AN ANODE COMPRISING INTERCALATING MATERIAL AND METAL SPECIES DISPERSED THEREIN
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
11497810
|
Filing Dt:
|
08/02/2006
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
CBRAM CELL AND CBRAM ARRAY, AND METHOD OF OPERATING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11541391
|
Filing Dt:
|
09/29/2006
|
Publication #:
|
|
Pub Dt:
|
04/10/2008
| | | | |
Title:
|
METHOD FOR FABRICATING A SOLID ELECTROLYTE MEMORY DEVICE AND SOLID ELECTROLYTE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
11549964
|
Filing Dt:
|
10/16/2006
|
Publication #:
|
|
Pub Dt:
|
05/24/2007
| | | | |
Title:
|
VOLTAGE REFERENCE CIRCUIT USING PROGRAMMABLE METALLIZATION CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11553393
|
Filing Dt:
|
10/26/2006
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
METHOD FOR PREVENTING OVER-ERASING OF UNUSED COLUMN REDUNDANT MEMORY CELLS IN A FLASH MEMORY HAVING SINGLE-TRANSISTOR MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
11555560
|
Filing Dt:
|
11/01/2006
|
Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
Title:
|
PROGRAMMABLE MEMORY DEVICE CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
11566555
|
Filing Dt:
|
12/04/2006
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
DEVICE AND METHOD FOR ACCESS TIME REDUCTION BY SPECULATIVELY DECODING NON-MEMORY READ COMMANDS ON A SERIAL INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
11611452
|
Filing Dt:
|
12/15/2006
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11688556
|
Filing Dt:
|
03/20/2007
|
Publication #:
|
|
Pub Dt:
|
09/13/2007
| | | | |
Title:
|
RESISTIVE MEMORY ARRANGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
11714091
|
Filing Dt:
|
03/05/2007
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE; METHOD OF MANUFACTURING A MEMORY CELL; SEMICONDUCTOR DEVICE; SEMICONDUCTOR PROCESSING DEVICE; INTEGRATED CIRCUIT HAVING A MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
11735864
|
Filing Dt:
|
04/16/2007
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT, METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT, MEMORY CELL ARRAY, MEMORY MODULE, AND DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2010
|
Application #:
|
11737236
|
Filing Dt:
|
04/19/2007
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
NOR AND NAND MEMORY ARRANGEMENT OF RESISTIVE MEMORY ELEMENTS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11746393
|
Filing Dt:
|
05/09/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
RESISTIVE SWITCHING ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
11784206
|
Filing Dt:
|
04/05/2007
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
Title:
|
METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT, AN INTEGRATED CIRCUIT, AND A MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11841591
|
Filing Dt:
|
08/20/2007
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
READ, WRITE, AND ERASE CIRCUIT FOR PROGRAMMABLE MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12026259
|
Filing Dt:
|
02/05/2008
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
A MEMORY DEVICE INCLUDING ELECTRICAL CIRCUIT CONFIGURED TO PROVIDE REVERSIBLE BIAS ACROSS THE PMC MEMORY CELL TO PERFORM ERASE AND WRITE FUNCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12205518
|
Filing Dt:
|
09/05/2008
|
Publication #:
|
|
Pub Dt:
|
03/11/2010
| | | | |
Title:
|
METHOD AND SYSTEM TO ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12508212
|
Filing Dt:
|
07/23/2009
|
Title:
|
INTEGRATED CIRCUITS HAVING PROGRAMMABLE METALLIZATION CELLS (PMCS) AND OPERATING METHODS THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
12566790
|
Filing Dt:
|
09/25/2009
|
Title:
|
VARIABLE IMPEDANCE MEMORY DEVICE HAVING SIMULTANEOUS PROGRAM AND ERASE, AND CORRESPONDING METHODS AND CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
12629531
|
Filing Dt:
|
12/02/2009
|
Title:
|
RECONFIGURABLE MEMORY ARRAYS HAVING PROGRAMMABLE IMPEDANCE ELEMENTS AND CORRESPONDING METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
12767552
|
Filing Dt:
|
04/26/2010
|
Title:
|
Conducting Bridge Random Access Memory (CBRAM) Device Structures
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2012
|
Application #:
|
12802506
|
Filing Dt:
|
06/07/2010
|
Title:
|
PMC-BASED NON-VOLATILE CAM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2011
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Application #:
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12913565
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Filing Dt:
|
10/27/2010
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Publication #:
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Pub Dt:
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02/17/2011
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Title:
|
METHOD FOR PRODUCING MEMORY HAVING A SOLID ELECTROLYTE MATERIAL REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
12980752
|
Filing Dt:
|
12/29/2010
|
Title:
|
METHODS AND CIRCUITS FOR TEMPERATURE VARYING WRITE OPERATIONS OF PROGRAMMABLE IMPEDANCE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
13052810
|
Filing Dt:
|
03/21/2011
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
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Title:
|
METHOD AND SYSTEM TO ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13114192
|
Filing Dt:
|
05/24/2011
|
Title:
|
CIRCUITS AND METHODS HAVING PROGRAMMABLE IMPEDANCE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13157713
|
Filing Dt:
|
06/10/2011
|
Title:
|
CIRCUITS HAVING PROGRAMMABLE IMPEDANCE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13242854
|
Filing Dt:
|
09/23/2011
|
Title:
|
VARIABLE IMPEDANCE MEMORY DEVICE STRUCTURE AND METHOD OF MANUFACTURE INCLUDING PROGRAMMABLE IMPEDANCE MEMORY CELLS AND METHODS OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13276763
|
Filing Dt:
|
10/19/2011
|
Title:
|
READ METHODS, CIRCUITS AND SYSTEMS FOR MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2015
|
Application #:
|
13315652
|
Filing Dt:
|
12/09/2011
|
Title:
|
MEMORY DEVICES, CIRCUITS AND METHODS HAVING DATA VALUES BASED ON DYNAMIC CHANGE IN MATERIAL PROPERTY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2015
|
Application #:
|
13336642
|
Filing Dt:
|
12/23/2011
|
Title:
|
RESISTIVE MEMORY DEVICES, CIRCUITS AND METHODS HAVING READ CURRENT LIMITING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13337004
|
Filing Dt:
|
12/23/2011
|
Title:
|
METHODS OF PROGRAMMING AND ERASING PROGRAMMABLE METALLIZATION CELLS (PMCS)
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13346749
|
Filing Dt:
|
01/10/2012
|
Publication #:
|
|
Pub Dt:
|
05/03/2012
| | | | |
Title:
|
MEMORY CELL DEVICE AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
13408367
|
Filing Dt:
|
02/29/2012
|
Title:
|
MEMORY DEVICES AND METHODS FOR READ AND WRITE OPERATION TO MEMORY ELEMENTS HAVING DYNAMIC CHANGE IN PROPERTY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13408797
|
Filing Dt:
|
02/29/2012
|
Title:
|
READ OPERATIONS AND CIRCUITS FOR MEMORY DEVICES HAVING PROGRAMMABLE ELEMENTS, INCLUDING PROGRAMMABLE RESISTANCE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13431951
|
Filing Dt:
|
03/27/2012
|
Title:
|
PROGRAMMABLE IMPEDANCE MEMORY ELEMENTS, METHODS OF MANUFACTURE, AND MEMORY DEVICES CONTAINING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13437906
|
Filing Dt:
|
04/02/2012
|
Title:
|
CIRCUITS AND METHODS FOR PLACING PROGRAMMABLE IMPEDANCE MEMORY ELEMENTS IN HIGH IMPEDANCE STATES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13445389
|
Filing Dt:
|
04/12/2012
|
Title:
|
VARIABLE IMPEDANCE MEMORY ELEMENT STRUCTURES, METHODS OF MANUFACTURE, AND MEMORY DEVICES CONTAINING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
13462659
|
Filing Dt:
|
05/02/2012
|
Title:
|
Resistive Switching Memories
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
13464895
|
Filing Dt:
|
05/04/2012
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
CONDUCTIVE FILAMENT BASED MEMORY ELEMENTS AND METHODS WITH IMPROVED DATA RETENTION AND/OR ENDURANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13464926
|
Filing Dt:
|
05/04/2012
|
Title:
|
MEMORY DEVICES, ARCHITECTURES AND METHODS FOR MEMORY ELEMENTS HAVING DYNAMIC CHANGE IN PROPERTY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2015
|
Application #:
|
13470030
|
Filing Dt:
|
05/11/2012
|
Publication #:
|
|
Pub Dt:
|
11/14/2013
| | | | |
Title:
|
METHOD OF OPERATING A RESISTIVE MEMORY DEVICE WITH A RAMP-UP/RAMP-DOWN PROGRAM/ERASE PULSE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13470286
|
Filing Dt:
|
05/12/2012
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
Title:
|
CONTACT STRUCTURE AND METHOD FOR VARIABLE IMPEDANCE MEMORY ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13488392
|
Filing Dt:
|
06/04/2012
|
Title:
|
ERASE AND SOFT PROGRAM WITHIN THE ERASE OPERATION FOR A HIGH SPEED RESISTIVE SWITCHING MEMORY OPERATION WITH CONTROLLED ERASED STATES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13517653
|
Filing Dt:
|
06/14/2012
|
Title:
|
Resistive Switching Devices Having A Buffer Layer and Methods of Formation Thereof
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13545792
|
Filing Dt:
|
07/10/2012
|
Title:
|
METHODS OF PROGRAMMING AND ERASING PROGRAMMABLE METALLIZATION CELLS (PMCs)
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13545958
|
Filing Dt:
|
07/10/2012
|
Title:
|
PROGRAMMABLE MEMORY ELEMENTS, DEVICES AND METHODS HAVING PHYSICALLY LOCALIZED STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2015
|
Application #:
|
13548429
|
Filing Dt:
|
07/13/2012
|
Title:
|
PROGRAMMABLE WINDOW OF OPERATION FOR CBRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13548470
|
Filing Dt:
|
07/13/2012
|
Title:
|
CBRAM/RERAM WITH IMPROVED PROGRAM AND ERASE ALGORITHMS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13558296
|
Filing Dt:
|
07/25/2012
|
Publication #:
|
|
Pub Dt:
|
03/14/2013
| | | | |
Title:
|
Resistive Switching Devices Having Alloyed Electrodes And Methods of Formation Thereof
|
|