Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 055213/0924 | |
| Pages: | 4 |
| | Recorded: | 02/04/2021 | | |
Attorney Dkt #: | PN148336HTKS |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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09/07/2010
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Application #:
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12163581
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Filing Dt:
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06/27/2008
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Publication #:
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Pub Dt:
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12/04/2008
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Title:
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SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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12848652
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Filing Dt:
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08/02/2010
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Publication #:
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Pub Dt:
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11/25/2010
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Title:
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WAFER LEVEL CHIP SCALE PACKAGE
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Patent #:
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Issue Dt:
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06/17/2014
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Application #:
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13397876
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Filing Dt:
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02/16/2012
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Publication #:
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Pub Dt:
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06/14/2012
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Title:
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WAFER-LEVEL INTERCONNECT FOR HIGH MECHANICAL RELIABILITY APPLICATIONS
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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13457311
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Filing Dt:
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04/26/2012
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Publication #:
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Pub Dt:
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09/13/2012
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Title:
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SOLDER BUMP INTERCONNECT
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Patent #:
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Issue Dt:
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04/28/2015
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Application #:
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13572376
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Filing Dt:
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08/10/2012
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Publication #:
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Pub Dt:
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02/14/2013
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Title:
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THIN FILM STRUCTURE FOR HIGH DENSITY INDUCTORS AND REDISTRIBUTION IN WAFER LEVEL PACKAGING
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Patent #:
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Issue Dt:
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03/17/2015
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Application #:
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13789411
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Filing Dt:
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03/07/2013
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Publication #:
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Pub Dt:
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12/12/2013
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Title:
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METHOD FOR APPLYING A FINAL METAL LAYER FOR WAFER LEVEL PACKAGING AND ASSOCIATED DEVICE
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Patent #:
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Issue Dt:
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04/18/2017
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Application #:
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13826987
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Filing Dt:
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03/14/2013
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Publication #:
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Pub Dt:
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08/01/2013
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Title:
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METHOD FOR BUILDING VERTICAL PILLAR INTERCONNECT
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Patent #:
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Issue Dt:
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06/30/2015
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Application #:
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14039384
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Filing Dt:
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09/27/2013
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Publication #:
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Pub Dt:
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01/01/2015
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Title:
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ELECTROPLATING USING DIELECTRIC BRIDGES
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Assignee
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112 LONGTENG ROAD, ECONOMIC & TECHNICAL DEVELOPMENT ZONE |
KUNSHAN, JIANGSU, CHINA 215300 |
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Correspondence name and address
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GANG YU
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ACIP INTERNATIONAL, INC. 419 10TH ST,
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SF, CA 94103
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