Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 065943/0927 | |
| Pages: | 6 |
| | Recorded: | 12/22/2023 | | |
| Attorney Dkt #: | 389E03AGR |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
9
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Patent #:
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Issue Dt:
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05/01/2012
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Application #:
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12835699
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Filing Dt:
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07/13/2010
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Publication #:
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Pub Dt:
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01/19/2012
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Title:
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IMPROVED ON/OFF RATIO FOR NON-VOLATILE MEMORY DEVICE AND METHOD
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Patent #:
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Issue Dt:
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06/12/2012
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Application #:
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13158231
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Filing Dt:
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06/10/2011
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Publication #:
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Pub Dt:
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12/22/2011
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Title:
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PILLAR STRUCTURE FOR MEMORY DEVICE AND METHOD
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Patent #:
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Issue Dt:
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04/12/2016
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Application #:
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13625817
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Filing Dt:
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09/24/2012
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Publication #:
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Pub Dt:
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03/27/2014
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Title:
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ELECTRODE STRUCTURE FOR A NON-VOLATILE MEMORY DEVICE AND METHOD
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Patent #:
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Issue Dt:
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04/26/2016
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Application #:
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13756498
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Filing Dt:
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01/31/2013
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Title:
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RESISTIVE MEMORY CELL WITH SOLID STATE DIODE
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Patent #:
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Issue Dt:
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05/10/2016
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Application #:
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14214108
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Filing Dt:
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03/14/2014
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Title:
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SOAK TIME PROGRAMMING FOR TWO-TERMINAL MEMORY
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Patent #:
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Issue Dt:
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05/31/2016
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Application #:
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14469746
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Filing Dt:
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08/27/2014
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Title:
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MEMORY ARRAY WITH EMBEDDED SOURCE LINE DRIVER AND IMPROVED VOLTAGE REGULARITY
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Patent #:
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Issue Dt:
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06/07/2016
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Application #:
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14643832
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Filing Dt:
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03/10/2015
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Publication #:
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Pub Dt:
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07/02/2015
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Title:
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THREE DIMENSION PROGRAMMABLE RESISTIVE RANDOM ACCESSED MEMORY ARRAY WITH SHARED BITLINE AND METHOD
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Patent #:
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Issue Dt:
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08/18/2020
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Application #:
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15486529
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Filing Dt:
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04/13/2017
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Title:
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MEMORY STACK LINER COMPRISING DIELECTRIC BLOCK LAYER MATERIAL
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Patent #:
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Issue Dt:
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03/31/2020
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Application #:
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15676231
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Filing Dt:
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08/14/2017
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Publication #:
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Pub Dt:
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03/01/2018
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Title:
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RESISTIVE MEMORY CELL WITH INTRINSIC CURRENT CONTROL
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Assignee
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| ROOM 304, BUILDING 13, NO. 1211, HONGYIN ROAD, |
| LINGANG NEW AREA, CHINA (SHANGHAI) PILOT FREE TRADE ZONE |
| SHANGHAI, CHINA 201306 |
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Correspondence name and address
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HOLDER PATEL DRENNAN
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216 16TH STREET
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SUITE 1350
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DENVER, CO 80202
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