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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	015621/0932			Pages:	3
		Recorded:	01/27/2005
Attorney Dkt #:	UMC
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 39

Patent #:	6409129	Issue Dt:	06/25/2002	Application #:	09654228	Filing Dt:	09/02/2000
Title:	FIXING DEVICE FOR SETTING ANTI-SHOCK FOOT STAND

Patent #:	6486059	Issue Dt:	11/26/2002	Application #:	09841568	Filing Dt:	04/19/2001
Publication #:	US20020155695	Pub Dt:	10/24/2002
Title:	DUAL DAMASCENE PROCESS USING AN OXIDE LINER FOR A DIELECTRIC BARRIER LAYER

Patent #:	6516814	Issue Dt:	02/11/2003	Application #:	09847319	Filing Dt:	05/03/2001
Publication #:	US20020162569	Pub Dt:	11/07/2002
Title:	METHOD OF RAPID PREVENTION OF PARTICLE POLLUTION IN PRE-CLEAN CHAMBERS

Patent #:	6537622	Issue Dt:	03/25/2003	Application #:	09848375	Filing Dt:	05/04/2001
Publication #:	US20020164435	Pub Dt:	11/07/2002
Title:	METHOD OF PREVENTION OF PARTICLE POLLUTION IN A PRE-CLEAN CHAMBER

Patent #:	6391713	Issue Dt:	05/21/2002	Application #:	09854872	Filing Dt:	05/14/2001
Title:	METHOD FOR FORMING A DUAL DAMASCENE STRUCTURE HAVING CAPACITORS

Patent #:	6521138	Issue Dt:	02/18/2003	Application #:	09873157	Filing Dt:	06/01/2001
Publication #:	US20020179568	Pub Dt:	12/05/2002
Title:	METHOD FOR MEASURING WIDTH OF BOTTOM UNDER CUT DURING ETCHING PROCESS

Patent #:	6338999	Issue Dt:	01/15/2002	Application #:	09880782	Filing Dt:	06/15/2001
Title:	Method for forming metal capacitors with a damascene process

Patent #:	6492226	Issue Dt:	12/10/2002	Application #:	09880849	Filing Dt:	06/15/2001
Publication #:	US20020192921	Pub Dt:	12/19/2002
Title:	METHOD FOR FORMING A METAL CAPACITOR IN A DAMASCENE PROCESS

Patent #:	6358792	Issue Dt:	03/19/2002	Application #:	09881101	Filing Dt:	06/15/2001
Title:	Method for fabricating metal capacitor

Patent #:	6410386	Issue Dt:	06/25/2002	Application #:	09881102	Filing Dt:	06/15/2001
Title:	METHOD FOR FORMING A METAL CAPACITOR IN A DAMASCENE PROCESS

Patent #:	6521523	Issue Dt:	02/18/2003	Application #:	09881103	Filing Dt:	06/15/2001
Publication #:	US20020192940	Pub Dt:	12/19/2002
Title:	METHOD FOR FORMING SELECTIVE PROTECTION LAYERS ON COPPER INTERCONNECTS

Patent #:	6696222	Issue Dt:	02/24/2004	Application #:	09910876	Filing Dt:	07/24/2001
Publication #:	US20030044725	Pub Dt:	03/06/2003
Title:	DUAL DAMASCENE PROCESS USING METAL HARD MASK

Patent #:	6503835	Issue Dt:	01/07/2003	Application #:	09939606	Filing Dt:	08/28/2001
Title:	ORGANIC COPPER DIFFUSION BARRIER LAYER

Patent #:	6561204	Issue Dt:	05/13/2003	Application #:	09945634	Filing Dt:	09/05/2001
Publication #:	US20030042225	Pub Dt:	03/06/2003
Title:	APPARATUS AND METHOD FOR CLEANING WAFERS WITH CONTACT HOLES OR VIA HOLES

Patent #:	6651284	Issue Dt:	11/25/2003	Application #:	09973706	Filing Dt:	10/11/2001
Publication #:	US20030070242	Pub Dt:	04/17/2003
Title:	SCRUBBING ASSEMBLY FOR WAFER-CLEANING DEVICE

Patent #:	6596088	Issue Dt:	07/22/2003	Application #:	09985687	Filing Dt:	11/05/2001
Publication #:	US20030084922	Pub Dt:	05/08/2003
Title:	METHOD FOR REMOVING THE CIRCUMFERENTIAL EDGE OF A DIELECTRIC LAYER

Patent #:	6495877	Issue Dt:	12/17/2002	Application #:	10024289	Filing Dt:	12/21/2001
Publication #:	US20020190300	Pub Dt:	12/19/2002
Title:	METAL CAPACITORS WITH DAMASCENE STRUCTURES AND METHOD FOR FORMING THE SAME

Patent #:	6504205	Issue Dt:	01/07/2003	Application #:	10024711	Filing Dt:	12/21/2001
Publication #:	US20020190386	Pub Dt:	12/19/2002
Title:	METAL CAPACITORS WITH DAMASCENE STRUCTURES

Patent #:	6489193	Issue Dt:	12/03/2002	Application #:	10040442	Filing Dt:	01/09/2002
Title:	PROCESS FOR DEVICE ISOLATION

Patent #:	6548409	Issue Dt:	04/15/2003	Application #:	10076395	Filing Dt:	02/19/2002
Title:	METHOD OF REDUCING MICRO-SCRATCHES DURING TUNGSTEN CMP

Patent #:	6593225	Issue Dt:	07/15/2003	Application #:	10087773	Filing Dt:	03/05/2002
Title:	METHOD OF FORMING A STACKED DIELECTRIC LAYER ON A SEMICONDUCTOR SUBSTRATE HAVING METAL PATTERNS

Patent #:	6603167	Issue Dt:	08/05/2003	Application #:	10093531	Filing Dt:	03/11/2002
Publication #:	US20020190301	Pub Dt:	12/19/2002
Title:	CAPACITOR WITH LOWER ELECTRODE LOCATED AT THE SAME LEVEL AS AN INTERCONNECT LINE

Patent #:	6514815	Issue Dt:	02/04/2003	Application #:	10093538	Filing Dt:	03/11/2002
Publication #:	US20020192922	Pub Dt:	12/19/2002
Title:	METHOD FOR FABRICATING POLYSILICON CAPACITOR

Patent #:	6509238	Issue Dt:	01/21/2003	Application #:	10100676	Filing Dt:	03/18/2002
Title:	METHOD FOR MANUFACTURING A MOS DEVICE WITH IMPROVED WELL CONTROL STABILITY

Patent #:	6512260	Issue Dt:	01/28/2003	Application #:	10107482	Filing Dt:	03/28/2002
Publication #:	US20020190299	Pub Dt:	12/19/2002
Title:	METAL CAPACITOR IN DAMASCENE STRUCTURES

Patent #:	6483142	Issue Dt:	11/19/2002	Application #:	10108611	Filing Dt:	03/27/2002
Publication #:	US20020167090	Pub Dt:	11/14/2002
Title:	DUAL DAMASCENE STRUCTURE HAVING CAPACITORS

Patent #:	6696354	Issue Dt:	02/24/2004	Application #:	10131099	Filing Dt:	04/25/2002
Publication #:	US20030228742	Pub Dt:	12/11/2003
Title:	METHOD OF FORMING SALICIDE

Patent #:	6649512	Issue Dt:	11/18/2003	Application #:	10165739	Filing Dt:	06/07/2002
Publication #:	US20030228750	Pub Dt:	12/11/2003
Title:	METHOD FOR IMPROVING ADHESION OF A LOW K DIELECTRIC TO A BARRIER LAYER

Patent #:	6495448	Issue Dt:	12/17/2002	Application #:	10165794	Filing Dt:	06/07/2002
Title:	DUAL DAMASCENE PROCESS

Patent #:	NONE	Issue Dt:		Application #:	10230062	Filing Dt:	08/29/2002
Publication #:	US20040054543	Pub Dt:	03/18/2004
Title:	Storage and management method for a multi-floor stocker system

Patent #:	6743690	Issue Dt:	06/01/2004	Application #:	10237605	Filing Dt:	09/10/2002
Publication #:	US20040048438	Pub Dt:	03/11/2004
Title:	METHOD OF FORMING A METAL-OXIDE SEMICONDUCTOR TRANSISTOR

Patent #:	6784075	Issue Dt:	08/31/2004	Application #:	10237608	Filing Dt:	09/10/2002
Publication #:	US20040048442	Pub Dt:	03/11/2004
Title:	METHOD OF FORMING SHALLOW TRENCH ISOLATION IN A SEMICONDUCTOR SUBSTRATE

Patent #:	6720235	Issue Dt:	04/13/2004	Application #:	10237693	Filing Dt:	09/10/2002
Publication #:	US20040048443	Pub Dt:	03/11/2004
Title:	METHOD OF FORMING SHALLOW TRENCH ISOLATION IN A SEMICONDUCTOR SUBSTRATE

Patent #:	6727160	Issue Dt:	04/27/2004	Application #:	10270348	Filing Dt:	10/15/2002
Publication #:	US20040072400	Pub Dt:	04/15/2004
Title:	METHOD OF FORMING A SHALLOW TRENCH ISOLATION STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	10321565	Filing Dt:	12/18/2002
Publication #:	US20040121604	Pub Dt:	06/24/2004
Title:	Method of etching a low-k dielectric layer

Patent #:	NONE	Issue Dt:		Application #:	10372842	Filing Dt:	02/26/2003
Publication #:	US20040166691	Pub Dt:	08/26/2004
Title:	Method of etching a metal line

Patent #:	7076707	Issue Dt:	07/11/2006	Application #:	10401701	Filing Dt:	03/31/2003
Publication #:	US20040181722	Pub Dt:	09/16/2004
Title:	METHODOLOGY OF LOCATING FAULTS OF SCAN CHAINS IN LOGIC INTEGRATED CIRCUITS

Patent #:	NONE	Issue Dt:		Application #:	10446871	Filing Dt:	05/29/2003
Publication #:	US20040241948	Pub Dt:	12/02/2004
Title:	METHOD OF FABRICATING STACKED GATE DIELECTRIC LAYER

Patent #:	6979367	Issue Dt:	12/27/2005	Application #:	10637598	Filing Dt:	08/11/2003
Publication #:	US20050037616	Pub Dt:	02/17/2005
Title:	METHOD OF IMPROVING SURFACE PLANARITY

Assignor

SILICON INTEGRATED SYSTEMS CORP.

Exec Dt:

01/26/2005

Assignee

UNITED MICROELECTRONICS CORP.

NO. 3, LI-HSIN RD. II

SCIENCE-BASED INDUSTRIAL PARK

HSINCHU, TAIWAN R.O.C.

Correspondence name and address
	J.C. PATENTS
	JIAWEI HUANG
	4 VENTURE, SUITE 250
	IRVINE, CA 92618

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